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mozglue/build/SSE.cpp@97036ab72558 (annotated)

mozglue/build/SSE.cpp

Tue, 06 Jan 2015 21:39:09 +0100

author
Michael Schloh von Bennewitz <michael@schloh.com>
date
Tue, 06 Jan 2015 21:39:09 +0100
branch
TOR_BUG_9701
changeset 8
97036ab72558
permissions
-rw-r--r--

Conditionally force memory storage according to privacy.thirdparty.isolate;
This solves Tor bug #9701, complying with disk avoidance documented in
https://www.torproject.org/projects/torbrowser/design/#disk-avoidance.

michael@0 1 /* vim: set shiftwidth=4 tabstop=8 autoindent cindent expandtab: */
michael@0 2 /* This Source Code Form is subject to the terms of the Mozilla Public
michael@0 3 * License, v. 2.0. If a copy of the MPL was not distributed with this
michael@0 4 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
michael@0 5
michael@0 6 /* compile-time and runtime tests for whether to use SSE instructions */
michael@0 7
michael@0 8 #include "SSE.h"
michael@0 9
michael@0 10 namespace {
michael@0 11
michael@0 12 // SSE.h has parallel #ifs which declare MOZILLA_SSE_HAVE_CPUID_DETECTION.
michael@0 13 // We can't declare these functions in the header file, however, because
michael@0 14 // <intrin.h> conflicts with <windows.h> on MSVC 2005, and some files want to
michael@0 15 // include both SSE.h and <windows.h>.
michael@0 16
michael@0 17 #ifdef HAVE_CPUID_H
michael@0 18
michael@0 19 // cpuid.h is available on gcc 4.3 and higher on i386 and x86_64
michael@0 20 #include <cpuid.h>
michael@0 21
michael@0 22 enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
michael@0 23
michael@0 24 static bool
michael@0 25 has_cpuid_bit(unsigned int level, CPUIDRegister reg, unsigned int bit)
michael@0 26 {
michael@0 27 unsigned int regs[4];
michael@0 28 return __get_cpuid(level, &regs[0], &regs[1], &regs[2], &regs[3]) &&
michael@0 29 (regs[reg] & bit);
michael@0 30 }
michael@0 31
michael@0 32 #elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_AMD64))
michael@0 33
michael@0 34 // MSVC 2005 or newer on x86-32 or x86-64
michael@0 35 #include <intrin.h>
michael@0 36
michael@0 37 enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
michael@0 38
michael@0 39 static bool
michael@0 40 has_cpuid_bit(unsigned int level, CPUIDRegister reg, unsigned int bit)
michael@0 41 {
michael@0 42 // Check that the level in question is supported.
michael@0 43 int regs[4];
michael@0 44 __cpuid(regs, level & 0x80000000u);
michael@0 45 if (unsigned(regs[0]) < level)
michael@0 46 return false;
michael@0 47
michael@0 48 __cpuid(regs, level);
michael@0 49 return !!(unsigned(regs[reg]) & bit);
michael@0 50 }
michael@0 51
michael@0 52 #elif defined(__SUNPRO_CC) && (defined(__i386) || defined(__x86_64__))
michael@0 53
michael@0 54 enum CPUIDRegister { eax = 0, ebx = 1, ecx = 2, edx = 3 };
michael@0 55
michael@0 56 #ifdef __i386
michael@0 57 static void
michael@0 58 moz_cpuid(int CPUInfo[4], int InfoType)
michael@0 59 {
michael@0 60 asm (
michael@0 61 "xchg %esi, %ebx\n"
michael@0 62 "cpuid\n"
michael@0 63 "movl %eax, (%edi)\n"
michael@0 64 "movl %ebx, 4(%edi)\n"
michael@0 65 "movl %ecx, 8(%edi)\n"
michael@0 66 "movl %edx, 12(%edi)\n"
michael@0 67 "xchg %esi, %ebx\n"
michael@0 68 :
michael@0 69 : "a"(InfoType), // %eax
michael@0 70 "D"(CPUInfo) // %edi
michael@0 71 : "%ecx", "%edx", "%esi"
michael@0 72 );
michael@0 73 }
michael@0 74 #else
michael@0 75 static void
michael@0 76 moz_cpuid(int CPUInfo[4], int InfoType)
michael@0 77 {
michael@0 78 asm (
michael@0 79 "xchg %rsi, %rbx\n"
michael@0 80 "cpuid\n"
michael@0 81 "movl %eax, (%rdi)\n"
michael@0 82 "movl %ebx, 4(%rdi)\n"
michael@0 83 "movl %ecx, 8(%rdi)\n"
michael@0 84 "movl %edx, 12(%rdi)\n"
michael@0 85 "xchg %rsi, %rbx\n"
michael@0 86 :
michael@0 87 : "a"(InfoType), // %eax
michael@0 88 "D"(CPUInfo) // %rdi
michael@0 89 : "%ecx", "%edx", "%rsi"
michael@0 90 );
michael@0 91 }
michael@0 92 #endif
michael@0 93
michael@0 94 static bool
michael@0 95 has_cpuid_bit(unsigned int level, CPUIDRegister reg, unsigned int bit)
michael@0 96 {
michael@0 97 // Check that the level in question is supported.
michael@0 98 volatile int regs[4];
michael@0 99 moz_cpuid((int *)regs, level & 0x80000000u);
michael@0 100 if (unsigned(regs[0]) < level)
michael@0 101 return false;
michael@0 102
michael@0 103 moz_cpuid((int *)regs, level);
michael@0 104 return !!(unsigned(regs[reg]) & bit);
michael@0 105 }
michael@0 106
michael@0 107 #endif // end CPUID declarations
michael@0 108
michael@0 109 }
michael@0 110
michael@0 111 namespace mozilla {
michael@0 112
michael@0 113 namespace sse_private {
michael@0 114
michael@0 115 #if defined(MOZILLA_SSE_HAVE_CPUID_DETECTION)
michael@0 116
michael@0 117 #if !defined(MOZILLA_PRESUME_MMX)
michael@0 118 bool mmx_enabled = has_cpuid_bit(1u, edx, (1u<<23));
michael@0 119 #endif
michael@0 120
michael@0 121 #if !defined(MOZILLA_PRESUME_SSE)
michael@0 122 bool sse_enabled = has_cpuid_bit(1u, edx, (1u<<25));
michael@0 123 #endif
michael@0 124
michael@0 125 #if !defined(MOZILLA_PRESUME_SSE2)
michael@0 126 bool sse2_enabled = has_cpuid_bit(1u, edx, (1u<<26));
michael@0 127 #endif
michael@0 128
michael@0 129 #if !defined(MOZILLA_PRESUME_SSE3)
michael@0 130 bool sse3_enabled = has_cpuid_bit(1u, ecx, (1u<<0));
michael@0 131 #endif
michael@0 132
michael@0 133 #if !defined(MOZILLA_PRESUME_SSSE3)
michael@0 134 bool ssse3_enabled = has_cpuid_bit(1u, ecx, (1u<<9));
michael@0 135 #endif
michael@0 136
michael@0 137 #if !defined(MOZILLA_PRESUME_SSE4A)
michael@0 138 bool sse4a_enabled = has_cpuid_bit(0x80000001u, ecx, (1u<<6));
michael@0 139 #endif
michael@0 140
michael@0 141 #if !defined(MOZILLA_PRESUME_SSE4_1)
michael@0 142 bool sse4_1_enabled = has_cpuid_bit(1u, ecx, (1u<<19));
michael@0 143 #endif
michael@0 144
michael@0 145 #if !defined(MOZILLA_PRESUME_SSE4_2)
michael@0 146 bool sse4_2_enabled = has_cpuid_bit(1u, ecx, (1u<<20));
michael@0 147 #endif
michael@0 148
michael@0 149 #endif
michael@0 150
michael@0 151 } // namespace sse_private
michael@0 152 } // namespace mozilla

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