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media/libvpx/vp8/common/x86/recon_mmx.asm@ac0c01689b40 (annotated)

media/libvpx/vp8/common/x86/recon_mmx.asm

Thu, 15 Jan 2015 15:59:08 +0100

author

Michael Schloh von Bennewitz <michael@schloh.com>

date

Thu, 15 Jan 2015 15:59:08 +0100

branch

TOR_BUG_9701

changeset 10

ac0c01689b40

permissions

-rw-r--r--

Implement a real Private Browsing Mode condition by changing the API/ABI;
This solves Tor bug #9701, complying with disk avoidance documented in
https://www.torproject.org/projects/torbrowser/design/#disk-avoidance.

michael@0	1	;
michael@0	2	; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
michael@0	3	;
michael@0	4	; Use of this source code is governed by a BSD-style license
michael@0	5	; that can be found in the LICENSE file in the root of the source
michael@0	6	; tree. An additional intellectual property rights grant can be found
michael@0	7	; in the file PATENTS. All contributing project authors may
michael@0	8	; be found in the AUTHORS file in the root of the source tree.
michael@0	9	;
michael@0	10
michael@0	11
michael@0	12	%include "vpx_ports/x86_abi_support.asm"
michael@0	13
michael@0	14
michael@0	15	;void copy_mem8x8_mmx(
michael@0	16	; unsigned char *src,
michael@0	17	; int src_stride,
michael@0	18	; unsigned char *dst,
michael@0	19	; int dst_stride
michael@0	20	; )
michael@0	21	global sym(vp8_copy_mem8x8_mmx) PRIVATE
michael@0	22	sym(vp8_copy_mem8x8_mmx):
michael@0	23	push rbp
michael@0	24	mov rbp, rsp
michael@0	25	SHADOW_ARGS_TO_STACK 4
michael@0	26	push rsi
michael@0	27	push rdi
michael@0	28	; end prolog
michael@0	29
michael@0	30	mov rsi, arg(0) ;src;
michael@0	31	movq mm0, [rsi]
michael@0	32
michael@0	33	movsxd rax, dword ptr arg(1) ;src_stride;
michael@0	34	mov rdi, arg(2) ;dst;
michael@0	35
michael@0	36	movq mm1, [rsi+rax]
michael@0	37	movq mm2, [rsi+rax*2]
michael@0	38
michael@0	39	movsxd rcx, dword ptr arg(3) ;dst_stride
michael@0	40	lea rsi, [rsi+rax*2]
michael@0	41
michael@0	42	movq [rdi], mm0
michael@0	43	add rsi, rax
michael@0	44
michael@0	45	movq [rdi+rcx], mm1
michael@0	46	movq [rdi+rcx*2], mm2
michael@0	47
michael@0	48
michael@0	49	lea rdi, [rdi+rcx*2]
michael@0	50	movq mm3, [rsi]
michael@0	51
michael@0	52	add rdi, rcx
michael@0	53	movq mm4, [rsi+rax]
michael@0	54
michael@0	55	movq mm5, [rsi+rax*2]
michael@0	56	movq [rdi], mm3
michael@0	57
michael@0	58	lea rsi, [rsi+rax*2]
michael@0	59	movq [rdi+rcx], mm4
michael@0	60
michael@0	61	movq [rdi+rcx*2], mm5
michael@0	62	lea rdi, [rdi+rcx*2]
michael@0	63
michael@0	64	movq mm0, [rsi+rax]
michael@0	65	movq mm1, [rsi+rax*2]
michael@0	66
michael@0	67	movq [rdi+rcx], mm0
michael@0	68	movq [rdi+rcx*2],mm1
michael@0	69
michael@0	70	; begin epilog
michael@0	71	pop rdi
michael@0	72	pop rsi
michael@0	73	UNSHADOW_ARGS
michael@0	74	pop rbp
michael@0	75	ret
michael@0	76
michael@0	77
michael@0	78	;void copy_mem8x4_mmx(
michael@0	79	; unsigned char *src,
michael@0	80	; int src_stride,
michael@0	81	; unsigned char *dst,
michael@0	82	; int dst_stride
michael@0	83	; )
michael@0	84	global sym(vp8_copy_mem8x4_mmx) PRIVATE
michael@0	85	sym(vp8_copy_mem8x4_mmx):
michael@0	86	push rbp
michael@0	87	mov rbp, rsp
michael@0	88	SHADOW_ARGS_TO_STACK 4
michael@0	89	push rsi
michael@0	90	push rdi
michael@0	91	; end prolog
michael@0	92
michael@0	93	mov rsi, arg(0) ;src;
michael@0	94	movq mm0, [rsi]
michael@0	95
michael@0	96	movsxd rax, dword ptr arg(1) ;src_stride;
michael@0	97	mov rdi, arg(2) ;dst;
michael@0	98
michael@0	99	movq mm1, [rsi+rax]
michael@0	100	movq mm2, [rsi+rax*2]
michael@0	101
michael@0	102	movsxd rcx, dword ptr arg(3) ;dst_stride
michael@0	103	lea rsi, [rsi+rax*2]
michael@0	104
michael@0	105	movq [rdi], mm0
michael@0	106	movq [rdi+rcx], mm1
michael@0	107
michael@0	108	movq [rdi+rcx*2], mm2
michael@0	109	lea rdi, [rdi+rcx*2]
michael@0	110
michael@0	111	movq mm3, [rsi+rax]
michael@0	112	movq [rdi+rcx], mm3
michael@0	113
michael@0	114	; begin epilog
michael@0	115	pop rdi
michael@0	116	pop rsi
michael@0	117	UNSHADOW_ARGS
michael@0	118	pop rbp
michael@0	119	ret
michael@0	120
michael@0	121
michael@0	122	;void copy_mem16x16_mmx(
michael@0	123	; unsigned char *src,
michael@0	124	; int src_stride,
michael@0	125	; unsigned char *dst,
michael@0	126	; int dst_stride
michael@0	127	; )
michael@0	128	global sym(vp8_copy_mem16x16_mmx) PRIVATE
michael@0	129	sym(vp8_copy_mem16x16_mmx):
michael@0	130	push rbp
michael@0	131	mov rbp, rsp
michael@0	132	SHADOW_ARGS_TO_STACK 4
michael@0	133	push rsi
michael@0	134	push rdi
michael@0	135	; end prolog
michael@0	136
michael@0	137	mov rsi, arg(0) ;src;
michael@0	138	movsxd rax, dword ptr arg(1) ;src_stride;
michael@0	139
michael@0	140	mov rdi, arg(2) ;dst;
michael@0	141	movsxd rcx, dword ptr arg(3) ;dst_stride
michael@0	142
michael@0	143	movq mm0, [rsi]
michael@0	144	movq mm3, [rsi+8];
michael@0	145
michael@0	146	movq mm1, [rsi+rax]
michael@0	147	movq mm4, [rsi+rax+8]
michael@0	148
michael@0	149	movq mm2, [rsi+rax*2]
michael@0	150	movq mm5, [rsi+rax*2+8]
michael@0	151
michael@0	152	lea rsi, [rsi+rax*2]
michael@0	153	add rsi, rax
michael@0	154
michael@0	155	movq [rdi], mm0
michael@0	156	movq [rdi+8], mm3
michael@0	157
michael@0	158	movq [rdi+rcx], mm1
michael@0	159	movq [rdi+rcx+8], mm4
michael@0	160
michael@0	161	movq [rdi+rcx*2], mm2
michael@0	162	movq [rdi+rcx*2+8], mm5
michael@0	163
michael@0	164	lea rdi, [rdi+rcx*2]
michael@0	165	add rdi, rcx
michael@0	166
michael@0	167	movq mm0, [rsi]
michael@0	168	movq mm3, [rsi+8];
michael@0	169
michael@0	170	movq mm1, [rsi+rax]
michael@0	171	movq mm4, [rsi+rax+8]
michael@0	172
michael@0	173	movq mm2, [rsi+rax*2]
michael@0	174	movq mm5, [rsi+rax*2+8]
michael@0	175
michael@0	176	lea rsi, [rsi+rax*2]
michael@0	177	add rsi, rax
michael@0	178
michael@0	179	movq [rdi], mm0
michael@0	180	movq [rdi+8], mm3
michael@0	181
michael@0	182	movq [rdi+rcx], mm1
michael@0	183	movq [rdi+rcx+8], mm4
michael@0	184
michael@0	185	movq [rdi+rcx*2], mm2
michael@0	186	movq [rdi+rcx*2+8], mm5
michael@0	187
michael@0	188	lea rdi, [rdi+rcx*2]
michael@0	189	add rdi, rcx
michael@0	190
michael@0	191	movq mm0, [rsi]
michael@0	192	movq mm3, [rsi+8];
michael@0	193
michael@0	194	movq mm1, [rsi+rax]
michael@0	195	movq mm4, [rsi+rax+8]
michael@0	196
michael@0	197	movq mm2, [rsi+rax*2]
michael@0	198	movq mm5, [rsi+rax*2+8]
michael@0	199
michael@0	200	lea rsi, [rsi+rax*2]
michael@0	201	add rsi, rax
michael@0	202
michael@0	203	movq [rdi], mm0
michael@0	204	movq [rdi+8], mm3
michael@0	205
michael@0	206	movq [rdi+rcx], mm1
michael@0	207	movq [rdi+rcx+8], mm4
michael@0	208
michael@0	209	movq [rdi+rcx*2], mm2
michael@0	210	movq [rdi+rcx*2+8], mm5
michael@0	211
michael@0	212	lea rdi, [rdi+rcx*2]
michael@0	213	add rdi, rcx
michael@0	214
michael@0	215	movq mm0, [rsi]
michael@0	216	movq mm3, [rsi+8];
michael@0	217
michael@0	218	movq mm1, [rsi+rax]
michael@0	219	movq mm4, [rsi+rax+8]
michael@0	220
michael@0	221	movq mm2, [rsi+rax*2]
michael@0	222	movq mm5, [rsi+rax*2+8]
michael@0	223
michael@0	224	lea rsi, [rsi+rax*2]
michael@0	225	add rsi, rax
michael@0	226
michael@0	227	movq [rdi], mm0
michael@0	228	movq [rdi+8], mm3
michael@0	229
michael@0	230	movq [rdi+rcx], mm1
michael@0	231	movq [rdi+rcx+8], mm4
michael@0	232
michael@0	233	movq [rdi+rcx*2], mm2
michael@0	234	movq [rdi+rcx*2+8], mm5
michael@0	235
michael@0	236	lea rdi, [rdi+rcx*2]
michael@0	237	add rdi, rcx
michael@0	238
michael@0	239	movq mm0, [rsi]
michael@0	240	movq mm3, [rsi+8];
michael@0	241
michael@0	242	movq mm1, [rsi+rax]
michael@0	243	movq mm4, [rsi+rax+8]
michael@0	244
michael@0	245	movq mm2, [rsi+rax*2]
michael@0	246	movq mm5, [rsi+rax*2+8]
michael@0	247
michael@0	248	lea rsi, [rsi+rax*2]
michael@0	249	add rsi, rax
michael@0	250
michael@0	251	movq [rdi], mm0
michael@0	252	movq [rdi+8], mm3
michael@0	253
michael@0	254	movq [rdi+rcx], mm1
michael@0	255	movq [rdi+rcx+8], mm4
michael@0	256
michael@0	257	movq [rdi+rcx*2], mm2
michael@0	258	movq [rdi+rcx*2+8], mm5
michael@0	259
michael@0	260	lea rdi, [rdi+rcx*2]
michael@0	261	add rdi, rcx
michael@0	262
michael@0	263	movq mm0, [rsi]
michael@0	264	movq mm3, [rsi+8];
michael@0	265
michael@0	266	movq [rdi], mm0
michael@0	267	movq [rdi+8], mm3
michael@0	268
michael@0	269	; begin epilog
michael@0	270	pop rdi
michael@0	271	pop rsi
michael@0	272	UNSHADOW_ARGS
michael@0	273	pop rbp
michael@0	274	ret