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media/libvpx/vp8/encoder/arm/armv6/vp8_subtract_armv6.asm@ac0c01689b40 (annotated)

media/libvpx/vp8/encoder/arm/armv6/vp8_subtract_armv6.asm

Thu, 15 Jan 2015 15:59:08 +0100

author

Michael Schloh von Bennewitz <michael@schloh.com>

date

Thu, 15 Jan 2015 15:59:08 +0100

branch

TOR_BUG_9701

changeset 10

ac0c01689b40

permissions

-rw-r--r--

Implement a real Private Browsing Mode condition by changing the API/ABI;
This solves Tor bug #9701, complying with disk avoidance documented in
https://www.torproject.org/projects/torbrowser/design/#disk-avoidance.

michael@0	1	;
michael@0	2	; Copyright (c) 2011 The WebM project authors. All Rights Reserved.
michael@0	3	;
michael@0	4	; Use of this source code is governed by a BSD-style license
michael@0	5	; that can be found in the LICENSE file in the root of the source
michael@0	6	; tree. An additional intellectual property rights grant can be found
michael@0	7	; in the file PATENTS. All contributing project authors may
michael@0	8	; be found in the AUTHORS file in the root of the source tree.
michael@0	9	;
michael@0	10
michael@0	11
michael@0	12	EXPORT |vp8_subtract_mby_armv6|
michael@0	13	EXPORT |vp8_subtract_mbuv_armv6|
michael@0	14	EXPORT |vp8_subtract_b_armv6|
michael@0	15
michael@0	16	INCLUDE vp8_asm_enc_offsets.asm
michael@0	17
michael@0	18	ARM
michael@0	19	REQUIRE8
michael@0	20	PRESERVE8
michael@0	21
michael@0	22	AREA ||.text||, CODE, READONLY, ALIGN=2
michael@0	23
michael@0	24	; r0 BLOCK *be
michael@0	25	; r1 BLOCKD *bd
michael@0	26	; r2 int pitch
michael@0	27	|vp8_subtract_b_armv6| PROC
michael@0	28
michael@0	29	stmfd sp!, {r4-r9}
michael@0	30
michael@0	31	ldr r4, [r0, #vp8_block_base_src]
michael@0	32	ldr r5, [r0, #vp8_block_src]
michael@0	33	ldr r6, [r0, #vp8_block_src_diff]
michael@0	34
michael@0	35	ldr r3, [r4]
michael@0	36	ldr r7, [r0, #vp8_block_src_stride]
michael@0	37	add r3, r3, r5 ; src = *base_src + src
michael@0	38	ldr r8, [r1, #vp8_blockd_predictor]
michael@0	39
michael@0	40	mov r9, #4 ; loop count
michael@0	41
michael@0	42	loop_block
michael@0	43
michael@0	44	ldr r0, [r3], r7 ; src
michael@0	45	ldr r1, [r8], r2 ; pred
michael@0	46
michael@0	47	uxtb16 r4, r0 ; [s2 | s0]
michael@0	48	uxtb16 r5, r1 ; [p2 | p0]
michael@0	49	uxtb16 r0, r0, ror #8 ; [s3 | s1]
michael@0	50	uxtb16 r1, r1, ror #8 ; [p3 | p1]
michael@0	51
michael@0	52	usub16 r4, r4, r5 ; [d2 | d0]
michael@0	53	usub16 r5, r0, r1 ; [d3 | d1]
michael@0	54
michael@0	55	subs r9, r9, #1 ; decrement loop counter
michael@0	56
michael@0	57	pkhbt r0, r4, r5, lsl #16 ; [d1 | d0]
michael@0	58	pkhtb r1, r5, r4, asr #16 ; [d3 | d2]
michael@0	59
michael@0	60	str r0, [r6, #0] ; diff
michael@0	61	str r1, [r6, #4] ; diff
michael@0	62
michael@0	63	add r6, r6, r2, lsl #1 ; update diff pointer
michael@0	64	bne loop_block
michael@0	65
michael@0	66	ldmfd sp!, {r4-r9}
michael@0	67	mov pc, lr
michael@0	68
michael@0	69	ENDP
michael@0	70
michael@0	71
michael@0	72	; r0 short *diff
michael@0	73	; r1 unsigned char *usrc
michael@0	74	; r2 unsigned char *vsrc
michael@0	75	; r3 int src_stride
michael@0	76	; sp unsigned char *upred
michael@0	77	; sp unsigned char *vpred
michael@0	78	; sp int pred_stride
michael@0	79	|vp8_subtract_mbuv_armv6| PROC
michael@0	80
michael@0	81	stmfd sp!, {r4-r11}
michael@0	82
michael@0	83	add r0, r0, #512 ; set *diff point to Cb
michael@0	84	mov r4, #8 ; loop count
michael@0	85	ldr r5, [sp, #32] ; upred
michael@0	86	ldr r12, [sp, #40] ; pred_stride
michael@0	87
michael@0	88	; Subtract U block
michael@0	89	loop_u
michael@0	90	ldr r6, [r1] ; usrc (A)
michael@0	91	ldr r7, [r5] ; upred (A)
michael@0	92
michael@0	93	uxtb16 r8, r6 ; [s2 | s0] (A)
michael@0	94	uxtb16 r9, r7 ; [p2 | p0] (A)
michael@0	95	uxtb16 r10, r6, ror #8 ; [s3 | s1] (A)
michael@0	96	uxtb16 r11, r7, ror #8 ; [p3 | p1] (A)
michael@0	97
michael@0	98	usub16 r6, r8, r9 ; [d2 | d0] (A)
michael@0	99	usub16 r7, r10, r11 ; [d3 | d1] (A)
michael@0	100
michael@0	101	ldr r10, [r1, #4] ; usrc (B)
michael@0	102	ldr r11, [r5, #4] ; upred (B)
michael@0	103
michael@0	104	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (A)
michael@0	105	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (A)
michael@0	106
michael@0	107	str r8, [r0], #4 ; diff (A)
michael@0	108	uxtb16 r8, r10 ; [s2 | s0] (B)
michael@0	109	str r9, [r0], #4 ; diff (A)
michael@0	110
michael@0	111	uxtb16 r9, r11 ; [p2 | p0] (B)
michael@0	112	uxtb16 r10, r10, ror #8 ; [s3 | s1] (B)
michael@0	113	uxtb16 r11, r11, ror #8 ; [p3 | p1] (B)
michael@0	114
michael@0	115	usub16 r6, r8, r9 ; [d2 | d0] (B)
michael@0	116	usub16 r7, r10, r11 ; [d3 | d1] (B)
michael@0	117
michael@0	118	add r1, r1, r3 ; update usrc pointer
michael@0	119	add r5, r5, r12 ; update upred pointer
michael@0	120
michael@0	121	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (B)
michael@0	122	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (B)
michael@0	123
michael@0	124	str r8, [r0], #4 ; diff (B)
michael@0	125	subs r4, r4, #1 ; update loop counter
michael@0	126	str r9, [r0], #4 ; diff (B)
michael@0	127
michael@0	128	bne loop_u
michael@0	129
michael@0	130	ldr r5, [sp, #36] ; vpred
michael@0	131	mov r4, #8 ; loop count
michael@0	132
michael@0	133	; Subtract V block
michael@0	134	loop_v
michael@0	135	ldr r6, [r2] ; vsrc (A)
michael@0	136	ldr r7, [r5] ; vpred (A)
michael@0	137
michael@0	138	uxtb16 r8, r6 ; [s2 | s0] (A)
michael@0	139	uxtb16 r9, r7 ; [p2 | p0] (A)
michael@0	140	uxtb16 r10, r6, ror #8 ; [s3 | s1] (A)
michael@0	141	uxtb16 r11, r7, ror #8 ; [p3 | p1] (A)
michael@0	142
michael@0	143	usub16 r6, r8, r9 ; [d2 | d0] (A)
michael@0	144	usub16 r7, r10, r11 ; [d3 | d1] (A)
michael@0	145
michael@0	146	ldr r10, [r2, #4] ; vsrc (B)
michael@0	147	ldr r11, [r5, #4] ; vpred (B)
michael@0	148
michael@0	149	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (A)
michael@0	150	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (A)
michael@0	151
michael@0	152	str r8, [r0], #4 ; diff (A)
michael@0	153	uxtb16 r8, r10 ; [s2 | s0] (B)
michael@0	154	str r9, [r0], #4 ; diff (A)
michael@0	155
michael@0	156	uxtb16 r9, r11 ; [p2 | p0] (B)
michael@0	157	uxtb16 r10, r10, ror #8 ; [s3 | s1] (B)
michael@0	158	uxtb16 r11, r11, ror #8 ; [p3 | p1] (B)
michael@0	159
michael@0	160	usub16 r6, r8, r9 ; [d2 | d0] (B)
michael@0	161	usub16 r7, r10, r11 ; [d3 | d1] (B)
michael@0	162
michael@0	163	add r2, r2, r3 ; update vsrc pointer
michael@0	164	add r5, r5, r12 ; update vpred pointer
michael@0	165
michael@0	166	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (B)
michael@0	167	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (B)
michael@0	168
michael@0	169	str r8, [r0], #4 ; diff (B)
michael@0	170	subs r4, r4, #1 ; update loop counter
michael@0	171	str r9, [r0], #4 ; diff (B)
michael@0	172
michael@0	173	bne loop_v
michael@0	174
michael@0	175	ldmfd sp!, {r4-r11}
michael@0	176	bx lr
michael@0	177
michael@0	178	ENDP
michael@0	179
michael@0	180
michael@0	181	; r0 short *diff
michael@0	182	; r1 unsigned char *src
michael@0	183	; r2 int src_stride
michael@0	184	; r3 unsigned char *pred
michael@0	185	; sp int pred_stride
michael@0	186	|vp8_subtract_mby_armv6| PROC
michael@0	187
michael@0	188	stmfd sp!, {r4-r11}
michael@0	189	ldr r12, [sp, #32] ; pred_stride
michael@0	190	mov r4, #16
michael@0	191	loop
michael@0	192	ldr r6, [r1] ; src (A)
michael@0	193	ldr r7, [r3] ; pred (A)
michael@0	194
michael@0	195	uxtb16 r8, r6 ; [s2 | s0] (A)
michael@0	196	uxtb16 r9, r7 ; [p2 | p0] (A)
michael@0	197	uxtb16 r10, r6, ror #8 ; [s3 | s1] (A)
michael@0	198	uxtb16 r11, r7, ror #8 ; [p3 | p1] (A)
michael@0	199
michael@0	200	usub16 r6, r8, r9 ; [d2 | d0] (A)
michael@0	201	usub16 r7, r10, r11 ; [d3 | d1] (A)
michael@0	202
michael@0	203	ldr r10, [r1, #4] ; src (B)
michael@0	204	ldr r11, [r3, #4] ; pred (B)
michael@0	205
michael@0	206	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (A)
michael@0	207	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (A)
michael@0	208
michael@0	209	str r8, [r0], #4 ; diff (A)
michael@0	210	uxtb16 r8, r10 ; [s2 | s0] (B)
michael@0	211	str r9, [r0], #4 ; diff (A)
michael@0	212
michael@0	213	uxtb16 r9, r11 ; [p2 | p0] (B)
michael@0	214	uxtb16 r10, r10, ror #8 ; [s3 | s1] (B)
michael@0	215	uxtb16 r11, r11, ror #8 ; [p3 | p1] (B)
michael@0	216
michael@0	217	usub16 r6, r8, r9 ; [d2 | d0] (B)
michael@0	218	usub16 r7, r10, r11 ; [d3 | d1] (B)
michael@0	219
michael@0	220	ldr r10, [r1, #8] ; src (C)
michael@0	221	ldr r11, [r3, #8] ; pred (C)
michael@0	222
michael@0	223	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (B)
michael@0	224	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (B)
michael@0	225
michael@0	226	str r8, [r0], #4 ; diff (B)
michael@0	227	uxtb16 r8, r10 ; [s2 | s0] (C)
michael@0	228	str r9, [r0], #4 ; diff (B)
michael@0	229
michael@0	230	uxtb16 r9, r11 ; [p2 | p0] (C)
michael@0	231	uxtb16 r10, r10, ror #8 ; [s3 | s1] (C)
michael@0	232	uxtb16 r11, r11, ror #8 ; [p3 | p1] (C)
michael@0	233
michael@0	234	usub16 r6, r8, r9 ; [d2 | d0] (C)
michael@0	235	usub16 r7, r10, r11 ; [d3 | d1] (C)
michael@0	236
michael@0	237	ldr r10, [r1, #12] ; src (D)
michael@0	238	ldr r11, [r3, #12] ; pred (D)
michael@0	239
michael@0	240	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (C)
michael@0	241	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (C)
michael@0	242
michael@0	243	str r8, [r0], #4 ; diff (C)
michael@0	244	uxtb16 r8, r10 ; [s2 | s0] (D)
michael@0	245	str r9, [r0], #4 ; diff (C)
michael@0	246
michael@0	247	uxtb16 r9, r11 ; [p2 | p0] (D)
michael@0	248	uxtb16 r10, r10, ror #8 ; [s3 | s1] (D)
michael@0	249	uxtb16 r11, r11, ror #8 ; [p3 | p1] (D)
michael@0	250
michael@0	251	usub16 r6, r8, r9 ; [d2 | d0] (D)
michael@0	252	usub16 r7, r10, r11 ; [d3 | d1] (D)
michael@0	253
michael@0	254	add r1, r1, r2 ; update src pointer
michael@0	255	add r3, r3, r12 ; update pred pointer
michael@0	256
michael@0	257	pkhbt r8, r6, r7, lsl #16 ; [d1 | d0] (D)
michael@0	258	pkhtb r9, r7, r6, asr #16 ; [d3 | d2] (D)
michael@0	259
michael@0	260	str r8, [r0], #4 ; diff (D)
michael@0	261	subs r4, r4, #1 ; update loop counter
michael@0	262	str r9, [r0], #4 ; diff (D)
michael@0	263
michael@0	264	bne loop
michael@0	265
michael@0	266	ldmfd sp!, {r4-r11}
michael@0	267	bx lr
michael@0	268
michael@0	269	ENDP
michael@0	270
michael@0	271	END
michael@0	272