media/libyuv/util/cpuid.c@b8a032363ba2 (annotated)
media/libyuv/util/cpuid.c
Thu, 22 Jan 2015 13:21:57 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Thu, 22 Jan 2015 13:21:57 +0100
- branch
- TOR_BUG_9701
- changeset 15
- b8a032363ba2
- permissions
- -rw-r--r--
Incorporate requested changes from Mozilla in review:
https://bugzilla.mozilla.org/show_bug.cgi?id=1123480#c6
| michael@0 | 1 | /* |
| michael@0 | 2 | * Copyright 2012 The LibYuv Project Authors. All rights reserved. |
| michael@0 | 3 | * |
| michael@0 | 4 | * Use of this source code is governed by a BSD-style license |
| michael@0 | 5 | * that can be found in the LICENSE file in the root of the source |
| michael@0 | 6 | * tree. An additional intellectual property rights grant can be found |
| michael@0 | 7 | * in the file PATENTS. All contributing project authors may |
| michael@0 | 8 | * be found in the AUTHORS file in the root of the source tree. |
| michael@0 | 9 | */ |
| michael@0 | 10 | |
| michael@0 | 11 | #include <stdio.h> |
| michael@0 | 12 | #include <stdlib.h> |
| michael@0 | 13 | #include <string.h> |
| michael@0 | 14 | |
| michael@0 | 15 | #define INCLUDE_LIBYUV_COMPARE_H_ |
| michael@0 | 16 | #include "libyuv.h" |
| michael@0 | 17 | #include "./psnr.h" |
| michael@0 | 18 | #include "./ssim.h" |
| michael@0 | 19 | |
| michael@0 | 20 | int main(int argc, const char* argv[]) { |
| michael@0 | 21 | int cpu_flags = TestCpuFlag(-1); |
| michael@0 | 22 | int has_arm = TestCpuFlag(kCpuHasARM); |
| michael@0 | 23 | int has_mips = TestCpuFlag(kCpuHasMIPS); |
| michael@0 | 24 | int has_x86 = TestCpuFlag(kCpuHasX86); |
| michael@0 | 25 | #if defined(__i386__) || defined(__x86_64__) || \ |
| michael@0 | 26 | defined(_M_IX86) || defined(_M_X64) |
| michael@0 | 27 | if (has_x86) { |
| michael@0 | 28 | uint32 family, model, cpu_info[4]; |
| michael@0 | 29 | // Vendor ID: |
| michael@0 | 30 | // AuthenticAMD AMD processor |
| michael@0 | 31 | // CentaurHauls Centaur processor |
| michael@0 | 32 | // CyrixInstead Cyrix processor |
| michael@0 | 33 | // GenuineIntel Intel processor |
| michael@0 | 34 | // GenuineTMx86 Transmeta processor |
| michael@0 | 35 | // Geode by NSC National Semiconductor processor |
| michael@0 | 36 | // NexGenDriven NexGen processor |
| michael@0 | 37 | // RiseRiseRise Rise Technology processor |
| michael@0 | 38 | // SiS SiS SiS SiS processor |
| michael@0 | 39 | // UMC UMC UMC UMC processor |
| michael@0 | 40 | CpuId(0, 0, &cpu_info[0]); |
| michael@0 | 41 | cpu_info[0] = cpu_info[1]; // Reorder output |
| michael@0 | 42 | cpu_info[1] = cpu_info[3]; |
| michael@0 | 43 | cpu_info[3] = 0; |
| michael@0 | 44 | printf("Cpu Vendor: %s\n", (char*)(&cpu_info[0])); |
| michael@0 | 45 | |
| michael@0 | 46 | // CPU Family and Model |
| michael@0 | 47 | // 3:0 - Stepping |
| michael@0 | 48 | // 7:4 - Model |
| michael@0 | 49 | // 11:8 - Family |
| michael@0 | 50 | // 13:12 - Processor Type |
| michael@0 | 51 | // 19:16 - Extended Model |
| michael@0 | 52 | // 27:20 - Extended Family |
| michael@0 | 53 | CpuId(1, 0, &cpu_info[0]); |
| michael@0 | 54 | family = ((cpu_info[0] >> 8) & 0x0f) | ((cpu_info[0] >> 16) & 0xff0); |
| michael@0 | 55 | model = ((cpu_info[0] >> 4) & 0x0f) | ((cpu_info[0] >> 12) & 0xf0); |
| michael@0 | 56 | printf("Cpu Family %d (0x%x), Model %d (0x%x)\n", family, family, |
| michael@0 | 57 | model, model); |
| michael@0 | 58 | } |
| michael@0 | 59 | #endif |
| michael@0 | 60 | printf("Cpu Flags %x\n", cpu_flags); |
| michael@0 | 61 | printf("Has ARM %x\n", has_arm); |
| michael@0 | 62 | printf("Has MIPS %x\n", has_mips); |
| michael@0 | 63 | printf("Has X86 %x\n", has_x86); |
| michael@0 | 64 | if (has_arm) { |
| michael@0 | 65 | int has_neon = TestCpuFlag(kCpuHasNEON); |
| michael@0 | 66 | printf("Has NEON %x\n", has_neon); |
| michael@0 | 67 | } |
| michael@0 | 68 | if (has_mips) { |
| michael@0 | 69 | int has_mips_dsp = TestCpuFlag(kCpuHasMIPS_DSP); |
| michael@0 | 70 | int has_mips_dspr2 = TestCpuFlag(kCpuHasMIPS_DSPR2); |
| michael@0 | 71 | printf("Has MIPS DSP %x\n", has_mips_dsp); |
| michael@0 | 72 | printf("Has MIPS DSPR2 %x\n", has_mips_dspr2); |
| michael@0 | 73 | } |
| michael@0 | 74 | if (has_x86) { |
| michael@0 | 75 | int has_sse2 = TestCpuFlag(kCpuHasSSE2); |
| michael@0 | 76 | int has_ssse3 = TestCpuFlag(kCpuHasSSSE3); |
| michael@0 | 77 | int has_sse41 = TestCpuFlag(kCpuHasSSE41); |
| michael@0 | 78 | int has_sse42 = TestCpuFlag(kCpuHasSSE42); |
| michael@0 | 79 | int has_avx = TestCpuFlag(kCpuHasAVX); |
| michael@0 | 80 | int has_avx2 = TestCpuFlag(kCpuHasAVX2); |
| michael@0 | 81 | int has_erms = TestCpuFlag(kCpuHasERMS); |
| michael@0 | 82 | int has_fma3 = TestCpuFlag(kCpuHasFMA3); |
| michael@0 | 83 | printf("Has SSE2 %x\n", has_sse2); |
| michael@0 | 84 | printf("Has SSSE3 %x\n", has_ssse3); |
| michael@0 | 85 | printf("Has SSE4.1 %x\n", has_sse41); |
| michael@0 | 86 | printf("Has SSE4.2 %x\n", has_sse42); |
| michael@0 | 87 | printf("Has AVX %x\n", has_avx); |
| michael@0 | 88 | printf("Has AVX2 %x\n", has_avx2); |
| michael@0 | 89 | printf("Has ERMS %x\n", has_erms); |
| michael@0 | 90 | printf("Has FMA3 %x\n", has_fma3); |
| michael@0 | 91 | } |
| michael@0 | 92 | return 0; |
| michael@0 | 93 | } |
| michael@0 | 94 |
