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comparison: hal/gonk/tavarua.h

hal/gonk/tavarua.h

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1 #ifndef __LINUX_TAVARUA_H
2 #define __LINUX_TAVARUA_H
3
4 /* This is a Linux header generated by "make headers_install" */
5
6 #include <stdint.h>
7 #include <linux/ioctl.h>
8 #include <linux/videodev2.h>
9
10
11 #undef FM_DEBUG
12
13 /* constants */
14 #define RDS_BLOCKS_NUM (4)
15 #define BYTES_PER_BLOCK (3)
16 #define MAX_PS_LENGTH (96)
17 #define MAX_RT_LENGTH (64)
18
19 #define XFRDAT0 (0x20)
20 #define XFRDAT1 (0x21)
21 #define XFRDAT2 (0x22)
22
23 #define INTDET_PEEK_MSB (0x88)
24 #define INTDET_PEEK_LSB (0x26)
25
26 #define RMSSI_PEEK_MSB (0x88)
27 #define RMSSI_PEEK_LSB (0xA8)
28
29 #define MPX_DCC_BYPASS_POKE_MSB (0x88)
30 #define MPX_DCC_BYPASS_POKE_LSB (0xC0)
31
32 #define MPX_DCC_PEEK_MSB_REG1 (0x88)
33 #define MPX_DCC_PEEK_LSB_REG1 (0xC2)
34
35 #define MPX_DCC_PEEK_MSB_REG2 (0x88)
36 #define MPX_DCC_PEEK_LSB_REG2 (0xC3)
37
38 #define MPX_DCC_PEEK_MSB_REG3 (0x88)
39 #define MPX_DCC_PEEK_LSB_REG3 (0xC4)
40
41 #define ON_CHANNEL_TH_MSB (0x0B)
42 #define ON_CHANNEL_TH_LSB (0xA8)
43
44 #define OFF_CHANNEL_TH_MSB (0x0B)
45 #define OFF_CHANNEL_TH_LSB (0xAC)
46
47 #define ENF_200Khz (1)
48 #define SRCH200KHZ_OFFSET (7)
49 #define SRCH_MASK (1 << SRCH200KHZ_OFFSET)
50
51 /* Standard buffer size */
52 #define STD_BUF_SIZE (128)
53 /* Search direction */
54 #define SRCH_DIR_UP (0)
55 #define SRCH_DIR_DOWN (1)
56
57 /* control options */
58 #define CTRL_ON (1)
59 #define CTRL_OFF (0)
60
61 #define US_LOW_BAND (87.5)
62 #define US_HIGH_BAND (108)
63
64 /* constant for Tx */
65
66 #define MASK_PI (0x0000FFFF)
67 #define MASK_PI_MSB (0x0000FF00)
68 #define MASK_PI_LSB (0x000000FF)
69 #define MASK_PTY (0x0000001F)
70 #define MASK_TXREPCOUNT (0x0000000F)
71
72 #undef FMDBG
73 #ifdef FM_DEBUG
74 #define FMDBG(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
75 #else
76 #define FMDBG(fmt, args...)
77 #endif
78
79 #undef FMDERR
80 #define FMDERR(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
81
82 #undef FMDBG_I2C
83 #ifdef FM_DEBUG_I2C
84 #define FMDBG_I2C(fmt, args...) printk(KERN_INFO "fm_i2c: " fmt, ##args)
85 #else
86 #define FMDBG_I2C(fmt, args...)
87 #endif
88
89 /* function declarations */
90 /* FM Core audio paths. */
91 #define TAVARUA_AUDIO_OUT_ANALOG_OFF (0)
92 #define TAVARUA_AUDIO_OUT_ANALOG_ON (1)
93 #define TAVARUA_AUDIO_OUT_DIGITAL_OFF (0)
94 #define TAVARUA_AUDIO_OUT_DIGITAL_ON (1)
95
96 int tavarua_set_audio_path(int digital_on, int analog_on);
97
98 /* defines and enums*/
99
100 #define MARIMBA_A0 0x01010013
101 #define MARIMBA_2_1 0x02010204
102 #define BAHAMA_1_0 0x0302010A
103 #define BAHAMA_2_0 0x04020205
104 #define WAIT_TIMEOUT 2000
105 #define RADIO_INIT_TIME 15
106 #define TAVARUA_DELAY 10
107 /*
108 * The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
109 * 62.5 kHz otherwise.
110 * The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
111 * tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
112 * The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
113 */
114 #define FREQ_MUL (1000000 / 62.5)
115
116 enum v4l2_cid_private_tavarua_t {
117 V4L2_CID_PRIVATE_TAVARUA_SRCHMODE = (V4L2_CID_PRIVATE_BASE + 1),
118 V4L2_CID_PRIVATE_TAVARUA_SCANDWELL,
119 V4L2_CID_PRIVATE_TAVARUA_SRCHON,
120 V4L2_CID_PRIVATE_TAVARUA_STATE,
121 V4L2_CID_PRIVATE_TAVARUA_TRANSMIT_MODE,
122 V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,
123 V4L2_CID_PRIVATE_TAVARUA_REGION,
124 V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,
125 V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY,
126 V4L2_CID_PRIVATE_TAVARUA_SRCH_PI,
127 V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT,
128 V4L2_CID_PRIVATE_TAVARUA_EMPHASIS,
129 V4L2_CID_PRIVATE_TAVARUA_RDS_STD,
130 V4L2_CID_PRIVATE_TAVARUA_SPACING,
131 V4L2_CID_PRIVATE_TAVARUA_RDSON,
132 V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC,
133 V4L2_CID_PRIVATE_TAVARUA_LP_MODE,
134 V4L2_CID_PRIVATE_TAVARUA_ANTENNA,
135 V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,
136 V4L2_CID_PRIVATE_TAVARUA_PSALL,
137 /*v4l2 Tx controls*/
138 V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT,
139 V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME,
140 V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT,
141 V4L2_CID_PRIVATE_TAVARUA_IOVERC,
142 V4L2_CID_PRIVATE_TAVARUA_INTDET,
143 V4L2_CID_PRIVATE_TAVARUA_MPX_DCC,
144 V4L2_CID_PRIVATE_TAVARUA_AF_JUMP,
145 V4L2_CID_PRIVATE_TAVARUA_RSSI_DELTA,
146 V4L2_CID_PRIVATE_TAVARUA_HLSI,
147
148 /*
149 * Here we have IOCTl's that are specific to IRIS
150 * (V4L2_CID_PRIVATE_BASE + 0x1E to V4L2_CID_PRIVATE_BASE + 0x28)
151 */
152 V4L2_CID_PRIVATE_SOFT_MUTE,/* 0x800001E*/
153 V4L2_CID_PRIVATE_RIVA_ACCS_ADDR,
154 V4L2_CID_PRIVATE_RIVA_ACCS_LEN,
155 V4L2_CID_PRIVATE_RIVA_PEEK,
156 V4L2_CID_PRIVATE_RIVA_POKE,
157 V4L2_CID_PRIVATE_SSBI_ACCS_ADDR,
158 V4L2_CID_PRIVATE_SSBI_PEEK,
159 V4L2_CID_PRIVATE_SSBI_POKE,
160 V4L2_CID_PRIVATE_TX_TONE,
161 V4L2_CID_PRIVATE_RDS_GRP_COUNTERS,
162 V4L2_CID_PRIVATE_SET_NOTCH_FILTER,/* 0x8000028 */
163
164 V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH,/* 0x8000029 */
165 V4L2_CID_PRIVATE_TAVARUA_DO_CALIBRATION,/* 0x800002A : IRIS */
166 V4L2_CID_PRIVATE_TAVARUA_SRCH_ALGORITHM,/* 0x800002B */
167 V4L2_CID_PRIVATE_IRIS_GET_SINR, /* 0x800002C : IRIS */
168 V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, /* 0x800002D */
169 V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, /* 0x800002E */
170 V4L2_CID_PRIVATE_SINR_THRESHOLD, /* 0x800002F : IRIS */
171 V4L2_CID_PRIVATE_SINR_SAMPLES, /* 0x8000030 : IRIS */
172
173 };
174
175 enum tavarua_buf_t {
176 TAVARUA_BUF_SRCH_LIST,
177 TAVARUA_BUF_EVENTS,
178 TAVARUA_BUF_RT_RDS,
179 TAVARUA_BUF_PS_RDS,
180 TAVARUA_BUF_RAW_RDS,
181 TAVARUA_BUF_AF_LIST,
182 TAVARUA_BUF_MAX
183 };
184
185 enum tavarua_xfr_t {
186 TAVARUA_XFR_SYNC,
187 TAVARUA_XFR_ERROR,
188 TAVARUA_XFR_SRCH_LIST,
189 TAVARUA_XFR_RT_RDS,
190 TAVARUA_XFR_PS_RDS,
191 TAVARUA_XFR_AF_LIST,
192 TAVARUA_XFR_MAX
193 };
194
195 enum channel_spacing {
196 FM_CH_SPACE_200KHZ,
197 FM_CH_SPACE_100KHZ,
198 FM_CH_SPACE_50KHZ
199 };
200
201 enum step_size {
202 NO_SRCH200khz,
203 ENF_SRCH200khz
204 };
205
206 enum emphasis {
207 EMP_75,
208 EMP_50
209 };
210
211 enum rds_std {
212 RBDS_STD,
213 RDS_STD
214 };
215
216 /* offsets */
217 #define RAW_RDS 0x0F
218 #define RDS_BLOCK 3
219
220 /* registers*/
221 #define MARIMBA_XO_BUFF_CNTRL 0x07
222 #define RADIO_REGISTERS 0x30
223 #define XFR_REG_NUM 16
224 #define STATUS_REG_NUM 3
225
226 /* TX constants */
227 #define HEADER_SIZE 4
228 #define TX_ON 0x80
229 #define TAVARUA_TX_RT RDS_RT_0
230 #define TAVARUA_TX_PS RDS_PS_0
231
232 enum register_t {
233 STATUS_REG1 = 0,
234 STATUS_REG2,
235 STATUS_REG3,
236 RDCTRL,
237 FREQ,
238 TUNECTRL,
239 SRCHRDS1,
240 SRCHRDS2,
241 SRCHCTRL,
242 IOCTRL,
243 RDSCTRL,
244 ADVCTRL,
245 AUDIOCTRL,
246 RMSSI,
247 IOVERC,
248 AUDIOIND = 0x1E,
249 XFRCTRL,
250 FM_CTL0 = 0xFF,
251 LEAKAGE_CNTRL = 0xFE,
252 };
253 #define BAHAMA_RBIAS_CTL1 0x07
254 #define BAHAMA_FM_MODE_REG 0xFD
255 #define BAHAMA_FM_CTL1_REG 0xFE
256 #define BAHAMA_FM_CTL0_REG 0xFF
257 #define BAHAMA_FM_MODE_NORMAL 0x00
258 #define BAHAMA_LDO_DREG_CTL0 0xF0
259 #define BAHAMA_LDO_AREG_CTL0 0xF4
260
261 /* Radio Control */
262 #define RDCTRL_STATE_OFFSET 0
263 #define RDCTRL_STATE_MASK (3 << RDCTRL_STATE_OFFSET)
264 #define RDCTRL_BAND_OFFSET 2
265 #define RDCTRL_BAND_MASK (1 << RDCTRL_BAND_OFFSET)
266 #define RDCTRL_CHSPACE_OFFSET 3
267 #define RDCTRL_CHSPACE_MASK (3 << RDCTRL_CHSPACE_OFFSET)
268 #define RDCTRL_DEEMPHASIS_OFFSET 5
269 #define RDCTRL_DEEMPHASIS_MASK (1 << RDCTRL_DEEMPHASIS_OFFSET)
270 #define RDCTRL_HLSI_OFFSET 6
271 #define RDCTRL_HLSI_MASK (3 << RDCTRL_HLSI_OFFSET)
272 #define RDSAF_OFFSET 6
273 #define RDSAF_MASK (1 << RDSAF_OFFSET)
274
275 /* Tune Control */
276 #define TUNE_STATION 0x01
277 #define ADD_OFFSET (1 << 1)
278 #define SIGSTATE (1 << 5)
279 #define MOSTSTATE (1 << 6)
280 #define RDSSYNC (1 << 7)
281 /* Search Control */
282 #define SRCH_MODE_OFFSET 0
283 #define SRCH_MODE_MASK (7 << SRCH_MODE_OFFSET)
284 #define SRCH_DIR_OFFSET 3
285 #define SRCH_DIR_MASK (1 << SRCH_DIR_OFFSET)
286 #define SRCH_DWELL_OFFSET 4
287 #define SRCH_DWELL_MASK (7 << SRCH_DWELL_OFFSET)
288 #define SRCH_STATE_OFFSET 7
289 #define SRCH_STATE_MASK (1 << SRCH_STATE_OFFSET)
290
291 /* I/O Control */
292 #define IOC_HRD_MUTE 0x03
293 #define IOC_SFT_MUTE (1 << 2)
294 #define IOC_MON_STR (1 << 3)
295 #define IOC_SIG_BLND (1 << 4)
296 #define IOC_INTF_BLND (1 << 5)
297 #define IOC_ANTENNA (1 << 6)
298 #define IOC_ANTENNA_OFFSET 6
299 #define IOC_ANTENNA_MASK (1 << IOC_ANTENNA_OFFSET)
300
301 /* RDS Control */
302 #define RDS_ON 0x01
303 #define RDSCTRL_STANDARD_OFFSET 1
304 #define RDSCTRL_STANDARD_MASK (1 << RDSCTRL_STANDARD_OFFSET)
305
306 /* Advanced features controls */
307 #define RDSRTEN (1 << 3)
308 #define RDSPSEN (1 << 4)
309
310 /* Audio path control */
311 #define AUDIORX_ANALOG_OFFSET 0
312 #define AUDIORX_ANALOG_MASK (1 << AUDIORX_ANALOG_OFFSET)
313 #define AUDIORX_DIGITAL_OFFSET 1
314 #define AUDIORX_DIGITAL_MASK (1 << AUDIORX_DIGITAL_OFFSET)
315 #define AUDIOTX_OFFSET 2
316 #define AUDIOTX_MASK (1 << AUDIOTX_OFFSET)
317 #define I2SCTRL_OFFSET 3
318 #define I2SCTRL_MASK (1 << I2SCTRL_OFFSET)
319
320 /* Search options */
321 enum search_t {
322 SEEK,
323 SCAN,
324 SCAN_FOR_STRONG,
325 SCAN_FOR_WEAK,
326 RDS_SEEK_PTY,
327 RDS_SCAN_PTY,
328 RDS_SEEK_PI,
329 RDS_AF_JUMP,
330 };
331
332 enum audio_path {
333 FM_DIGITAL_PATH,
334 FM_ANALOG_PATH
335 };
336 #define SRCH_MODE 0x07
337 #define SRCH_DIR 0x08 /* 0-up 1-down */
338 #define SCAN_DWELL 0x70
339 #define SRCH_ON 0x80
340
341 /* RDS CONFIG */
342 #define RDS_CONFIG_PSALL 0x01
343
344 #define FM_ENABLE 0x22
345 #define SET_REG_FIELD(reg, val, offset, mask) \
346 (reg = (reg & ~mask) | (((val) << offset) & mask))
347 #define GET_REG_FIELD(reg, offset, mask) ((reg & mask) >> offset)
348 #define RSH_DATA(val, offset) ((val) >> (offset))
349 #define LSH_DATA(val, offset) ((val) << (offset))
350 #define GET_ABS_VAL(val) ((val) & (0xFF))
351
352 enum radio_state_t {
353 FM_OFF,
354 FM_RECV,
355 FM_TRANS,
356 FM_RESET,
357 };
358
359 #define XFRCTRL_WRITE (1 << 7)
360
361 /* Interrupt status */
362
363 /* interrupt register 1 */
364 #define READY (1 << 0) /* Radio ready after powerup or reset */
365 #define TUNE (1 << 1) /* Tune completed */
366 #define SEARCH (1 << 2) /* Search completed (read FREQ) */
367 #define SCANNEXT (1 << 3) /* Scanning for next station */
368 #define SIGNAL (1 << 4) /* Signal indicator change (read SIGSTATE) */
369 #define INTF (1 << 5) /* Interference cnt has fallen outside range */
370 #define SYNC (1 << 6) /* RDS sync state change (read RDSSYNC) */
371 #define AUDIO (1 << 7) /* Audio Control indicator (read AUDIOIND) */
372
373 /* interrupt register 2 */
374 #define RDSDAT (1 << 0) /* New unread RDS data group available */
375 #define BLOCKB (1 << 1) /* Block-B match condition exists */
376 #define PROGID (1 << 2) /* Block-A or Block-C matched stored PI value*/
377 #define RDSPS (1 << 3) /* New RDS Program Service Table available */
378 #define RDSRT (1 << 4) /* New RDS Radio Text available */
379 #define RDSAF (1 << 5) /* New RDS AF List available */
380 #define TXRDSDAT (1 << 6) /* Transmitted an RDS group */
381 #define TXRDSDONE (1 << 7) /* RDS raw group one-shot transmit completed */
382
383 /* interrupt register 3 */
384 #define TRANSFER (1 << 0) /* Data transfer (XFR) completed */
385 #define RDSPROC (1 << 1) /* Dynamic RDS Processing complete */
386 #define ERROR (1 << 7) /* Err occurred.Read code to determine cause */
387
388
389 #define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */
390 #define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */
391 /* Transfer */
392 enum tavarua_xfr_ctrl_t {
393 RDS_PS_0 = 0x01,
394 RDS_PS_1,
395 RDS_PS_2,
396 RDS_PS_3,
397 RDS_PS_4,
398 RDS_PS_5,
399 RDS_PS_6,
400 RDS_RT_0,
401 RDS_RT_1,
402 RDS_RT_2,
403 RDS_RT_3,
404 RDS_RT_4,
405 RDS_AF_0,
406 RDS_AF_1,
407 RDS_CONFIG,
408 RDS_TX_GROUPS,
409 RDS_COUNT_0,
410 RDS_COUNT_1,
411 RDS_COUNT_2,
412 RADIO_CONFIG,
413 RX_CONFIG,
414 RX_TIMERS,
415 RX_STATIONS_0,
416 RX_STATIONS_1,
417 INT_CTRL,
418 ERROR_CODE,
419 CHIPID,
420 CAL_DAT_0 = 0x20,
421 CAL_DAT_1,
422 CAL_DAT_2,
423 CAL_DAT_3,
424 CAL_CFG_0,
425 CAL_CFG_1,
426 DIG_INTF_0,
427 DIG_INTF_1,
428 DIG_AGC_0,
429 DIG_AGC_1,
430 DIG_AGC_2,
431 DIG_AUDIO_0,
432 DIG_AUDIO_1,
433 DIG_AUDIO_2,
434 DIG_AUDIO_3,
435 DIG_AUDIO_4,
436 DIG_RXRDS,
437 DIG_DCC,
438 DIG_SPUR,
439 DIG_MPXDCC,
440 DIG_PILOT,
441 DIG_DEMOD,
442 DIG_MOST,
443 DIG_TX_0,
444 DIG_TX_1,
445 PHY_TXGAIN = 0x3B,
446 PHY_CONFIG,
447 PHY_TXBLOCK,
448 PHY_TCB,
449 XFR_PEEK_MODE = 0x40,
450 XFR_POKE_MODE = 0xC0,
451 TAVARUA_XFR_CTRL_MAX
452 };
453
454 enum tavarua_evt_t {
455 TAVARUA_EVT_RADIO_READY,
456 TAVARUA_EVT_TUNE_SUCC,
457 TAVARUA_EVT_SEEK_COMPLETE,
458 TAVARUA_EVT_SCAN_NEXT,
459 TAVARUA_EVT_NEW_RAW_RDS,
460 TAVARUA_EVT_NEW_RT_RDS,
461 TAVARUA_EVT_NEW_PS_RDS,
462 TAVARUA_EVT_ERROR,
463 TAVARUA_EVT_BELOW_TH,
464 TAVARUA_EVT_ABOVE_TH,
465 TAVARUA_EVT_STEREO,
466 TAVARUA_EVT_MONO,
467 TAVARUA_EVT_RDS_AVAIL,
468 TAVARUA_EVT_RDS_NOT_AVAIL,
469 TAVARUA_EVT_NEW_SRCH_LIST,
470 TAVARUA_EVT_NEW_AF_LIST,
471 TAVARUA_EVT_TXRDSDAT,
472 TAVARUA_EVT_TXRDSDONE,
473 TAVARUA_EVT_RADIO_DISABLED
474 };
475
476 enum tavarua_region_t {
477 TAVARUA_REGION_US,
478 TAVARUA_REGION_EU,
479 TAVARUA_REGION_JAPAN,
480 TAVARUA_REGION_JAPAN_WIDE,
481 TAVARUA_REGION_OTHER
482 };
483
484 #endif /* __LINUX_TAVARUA_H */

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