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1 // Copyright (c) 2012 The Chromium Authors. All rights reserved. |
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2 // Use of this source code is governed by a BSD-style license that can be |
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3 // found in the LICENSE file. |
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4 |
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5 // For atomic operations on reference counts, see atomic_refcount.h. |
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6 // For atomic operations on sequence numbers, see atomic_sequence_num.h. |
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7 |
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8 // The routines exported by this module are subtle. If you use them, even if |
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9 // you get the code right, it will depend on careful reasoning about atomicity |
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10 // and memory ordering; it will be less readable, and harder to maintain. If |
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11 // you plan to use these routines, you should have a good reason, such as solid |
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12 // evidence that performance would otherwise suffer, or there being no |
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13 // alternative. You should assume only properties explicitly guaranteed by the |
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14 // specifications in this file. You are almost certainly _not_ writing code |
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15 // just for the x86; if you assume x86 semantics, x86 hardware bugs and |
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16 // implementations on other archtectures will cause your code to break. If you |
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17 // do not know what you are doing, avoid these routines, and use a Mutex. |
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18 // |
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19 // It is incorrect to make direct assignments to/from an atomic variable. |
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20 // You should use one of the Load or Store routines. The NoBarrier |
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21 // versions are provided when no barriers are needed: |
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22 // NoBarrier_Store() |
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23 // NoBarrier_Load() |
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24 // Although there are currently no compiler enforcement, you are encouraged |
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25 // to use these. |
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26 // |
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27 |
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28 #ifndef BASE_ATOMICOPS_H_ |
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29 #define BASE_ATOMICOPS_H_ |
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30 |
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31 #include "base/basictypes.h" |
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32 #include "build/build_config.h" |
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33 |
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34 #if defined(OS_WIN) && defined(ARCH_CPU_64_BITS) |
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35 // windows.h #defines this (only on x64). This causes problems because the |
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36 // public API also uses MemoryBarrier at the public name for this fence. So, on |
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37 // X64, undef it, and call its documented |
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38 // (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx) |
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39 // implementation directly. |
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40 #undef MemoryBarrier |
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41 #endif |
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42 |
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43 namespace base { |
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44 namespace subtle { |
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45 |
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46 typedef int32 Atomic32; |
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47 #ifdef ARCH_CPU_64_BITS |
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48 // We need to be able to go between Atomic64 and AtomicWord implicitly. This |
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49 // means Atomic64 and AtomicWord should be the same type on 64-bit. |
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50 #if defined(__ILP32__) || defined(OS_NACL) |
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51 // NaCl's intptr_t is not actually 64-bits on 64-bit! |
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52 // http://code.google.com/p/nativeclient/issues/detail?id=1162 |
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53 typedef int64_t Atomic64; |
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54 #else |
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55 typedef intptr_t Atomic64; |
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56 #endif |
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57 #endif |
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58 |
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59 // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or |
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60 // Atomic64 routines below, depending on your architecture. |
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61 typedef intptr_t AtomicWord; |
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62 |
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63 // Atomically execute: |
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64 // result = *ptr; |
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65 // if (*ptr == old_value) |
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66 // *ptr = new_value; |
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67 // return result; |
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68 // |
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69 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value". |
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70 // Always return the old value of "*ptr" |
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71 // |
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72 // This routine implies no memory barriers. |
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73 Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, |
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74 Atomic32 old_value, |
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75 Atomic32 new_value); |
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76 |
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77 // Atomically store new_value into *ptr, returning the previous value held in |
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78 // *ptr. This routine implies no memory barriers. |
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79 Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value); |
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80 |
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81 // Atomically increment *ptr by "increment". Returns the new value of |
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82 // *ptr with the increment applied. This routine implies no memory barriers. |
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83 Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment); |
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84 |
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85 Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, |
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86 Atomic32 increment); |
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87 |
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88 // These following lower-level operations are typically useful only to people |
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89 // implementing higher-level synchronization operations like spinlocks, |
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90 // mutexes, and condition-variables. They combine CompareAndSwap(), a load, or |
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91 // a store with appropriate memory-ordering instructions. "Acquire" operations |
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92 // ensure that no later memory access can be reordered ahead of the operation. |
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93 // "Release" operations ensure that no previous memory access can be reordered |
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94 // after the operation. "Barrier" operations have both "Acquire" and "Release" |
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95 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory |
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96 // access. |
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97 Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, |
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98 Atomic32 old_value, |
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99 Atomic32 new_value); |
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100 Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, |
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101 Atomic32 old_value, |
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102 Atomic32 new_value); |
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103 |
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104 void MemoryBarrier(); |
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105 void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value); |
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106 void Acquire_Store(volatile Atomic32* ptr, Atomic32 value); |
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107 void Release_Store(volatile Atomic32* ptr, Atomic32 value); |
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108 |
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109 Atomic32 NoBarrier_Load(volatile const Atomic32* ptr); |
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110 Atomic32 Acquire_Load(volatile const Atomic32* ptr); |
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111 Atomic32 Release_Load(volatile const Atomic32* ptr); |
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112 |
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113 // 64-bit atomic operations (only available on 64-bit processors). |
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114 #ifdef ARCH_CPU_64_BITS |
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115 Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, |
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116 Atomic64 old_value, |
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117 Atomic64 new_value); |
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118 Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value); |
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119 Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); |
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120 Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); |
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121 |
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122 Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, |
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123 Atomic64 old_value, |
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124 Atomic64 new_value); |
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125 Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, |
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126 Atomic64 old_value, |
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127 Atomic64 new_value); |
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128 void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value); |
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129 void Acquire_Store(volatile Atomic64* ptr, Atomic64 value); |
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130 void Release_Store(volatile Atomic64* ptr, Atomic64 value); |
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131 Atomic64 NoBarrier_Load(volatile const Atomic64* ptr); |
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132 Atomic64 Acquire_Load(volatile const Atomic64* ptr); |
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133 Atomic64 Release_Load(volatile const Atomic64* ptr); |
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134 #endif // ARCH_CPU_64_BITS |
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135 |
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136 } // namespace base::subtle |
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137 } // namespace base |
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138 |
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139 // Include our platform specific implementation. |
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140 #if defined(THREAD_SANITIZER) |
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141 #include "base/atomicops_internals_tsan.h" |
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142 #elif defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY) |
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143 #include "base/atomicops_internals_x86_msvc.h" |
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144 #elif defined(OS_MACOSX) |
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145 #include "base/atomicops_internals_mac.h" |
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146 #elif defined(OS_NACL) |
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147 #include "base/atomicops_internals_gcc.h" |
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148 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY) |
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149 #include "base/atomicops_internals_arm_gcc.h" |
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150 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY) |
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151 #include "base/atomicops_internals_x86_gcc.h" |
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152 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS_FAMILY) |
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153 #include "base/atomicops_internals_mips_gcc.h" |
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154 #else |
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155 #error "Atomic operations are not supported on your platform" |
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156 #endif |
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157 |
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158 // On some platforms we need additional declarations to make |
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159 // AtomicWord compatible with our other Atomic* types. |
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160 #if defined(OS_MACOSX) || defined(OS_OPENBSD) |
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161 #include "base/atomicops_internals_atomicword_compat.h" |
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162 #endif |
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163 |
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164 #endif // BASE_ATOMICOPS_H_ |