1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/media/libyuv/source/row_mips.cc Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,1029 @@
1.4 +/*
1.5 + * Copyright (c) 2012 The LibYuv project authors. All Rights Reserved.
1.6 + *
1.7 + * Use of this source code is governed by a BSD-style license
1.8 + * that can be found in the LICENSE file in the root of the source
1.9 + * tree. An additional intellectual property rights grant can be found
1.10 + * in the file PATENTS. All contributing project authors may
1.11 + * be found in the AUTHORS file in the root of the source tree.
1.12 + */
1.13 +
1.14 +#include "libyuv/row.h"
1.15 +
1.16 +#ifdef __cplusplus
1.17 +namespace libyuv {
1.18 +extern "C" {
1.19 +#endif
1.20 +
1.21 +// The following are available on Mips platforms:
1.22 +#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__)
1.23 +
1.24 +#include <sgidefs.h>
1.25 +
1.26 +#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
1.27 +#define HAS_MIPS_PREFETCH 1
1.28 +#endif
1.29 +
1.30 +#ifdef HAS_COPYROW_MIPS
1.31 +void CopyRow_MIPS(const uint8* src, uint8* dst, int count) {
1.32 + __asm__ __volatile__ (
1.33 + ".set noreorder \n"
1.34 + ".set noat \n"
1.35 + "slti $at, %[count], 8 \n"
1.36 + "bne $at ,$zero, $last8 \n"
1.37 + "xor $t8, %[src], %[dst] \n"
1.38 + "andi $t8, $t8, 0x3 \n"
1.39 +
1.40 + "bne $t8, $zero, unaligned \n"
1.41 + "negu $a3, %[dst] \n"
1.42 + // make dst/src aligned
1.43 + "andi $a3, $a3, 0x3 \n"
1.44 + "beq $a3, $zero, $chk16w \n"
1.45 + // word-aligned now count is the remining bytes count
1.46 + "subu %[count], %[count], $a3 \n"
1.47 +
1.48 + "lwr $t8, 0(%[src]) \n"
1.49 + "addu %[src], %[src], $a3 \n"
1.50 + "swr $t8, 0(%[dst]) \n"
1.51 + "addu %[dst], %[dst], $a3 \n"
1.52 +
1.53 + // Now the dst/src are mutually word-aligned with word-aligned addresses
1.54 + "$chk16w: \n"
1.55 + "andi $t8, %[count], 0x3f \n" // whole 64-B chunks?
1.56 + // t8 is the byte count after 64-byte chunks
1.57 + "beq %[count], $t8, chk8w \n"
1.58 + // There will be at most 1 32-byte chunk after it
1.59 + "subu $a3, %[count], $t8 \n" // the reminder
1.60 + // Here a3 counts bytes in 16w chunks
1.61 + "addu $a3, %[dst], $a3 \n"
1.62 + // Now a3 is the final dst after 64-byte chunks
1.63 + "addu $t0, %[dst], %[count] \n"
1.64 + // t0 is the "past the end" address
1.65 +
1.66 + // When in the loop we exercise "pref 30,x(a1)", the a1+x should not be past
1.67 + // the "t0-32" address
1.68 + // This means: for x=128 the last "safe" a1 address is "t0-160"
1.69 + // Alternatively, for x=64 the last "safe" a1 address is "t0-96"
1.70 + // we will use "pref 30,128(a1)", so "t0-160" is the limit
1.71 + "subu $t9, $t0, 160 \n"
1.72 +#ifdef HAS_MIPS_PREFETCH
1.73 + // t9 is the "last safe pref 30,128(a1)" address
1.74 + "pref 0, 0(%[src]) \n" // first line of src
1.75 + "pref 0, 32(%[src]) \n" // second line of src
1.76 + "pref 0, 64(%[src]) \n"
1.77 + "pref 30, 32(%[dst]) \n"
1.78 +#endif
1.79 + // In case the a1 > t9 don't use "pref 30" at all
1.80 + "sgtu $v1, %[dst], $t9 \n"
1.81 + "bgtz $v1, $loop16w \n"
1.82 + "nop \n"
1.83 + // otherwise, start with using pref30
1.84 +#ifdef HAS_MIPS_PREFETCH
1.85 + "pref 30, 64(%[dst]) \n"
1.86 +#endif
1.87 + "$loop16w: \n"
1.88 +#ifdef HAS_MIPS_PREFETCH
1.89 + "pref 0, 96(%[src]) \n"
1.90 +#endif
1.91 + "lw $t0, 0(%[src]) \n"
1.92 + "bgtz $v1, $skip_pref30_96 \n" // skip
1.93 + "lw $t1, 4(%[src]) \n"
1.94 +#ifdef HAS_MIPS_PREFETCH
1.95 + "pref 30, 96(%[dst]) \n" // continue
1.96 +#endif
1.97 + "$skip_pref30_96: \n"
1.98 + "lw $t2, 8(%[src]) \n"
1.99 + "lw $t3, 12(%[src]) \n"
1.100 + "lw $t4, 16(%[src]) \n"
1.101 + "lw $t5, 20(%[src]) \n"
1.102 + "lw $t6, 24(%[src]) \n"
1.103 + "lw $t7, 28(%[src]) \n"
1.104 +#ifdef HAS_MIPS_PREFETCH
1.105 + "pref 0, 128(%[src]) \n"
1.106 +#endif
1.107 + // bring the next lines of src, addr 128
1.108 + "sw $t0, 0(%[dst]) \n"
1.109 + "sw $t1, 4(%[dst]) \n"
1.110 + "sw $t2, 8(%[dst]) \n"
1.111 + "sw $t3, 12(%[dst]) \n"
1.112 + "sw $t4, 16(%[dst]) \n"
1.113 + "sw $t5, 20(%[dst]) \n"
1.114 + "sw $t6, 24(%[dst]) \n"
1.115 + "sw $t7, 28(%[dst]) \n"
1.116 + "lw $t0, 32(%[src]) \n"
1.117 + "bgtz $v1, $skip_pref30_128 \n" // skip pref 30,128(a1)
1.118 + "lw $t1, 36(%[src]) \n"
1.119 +#ifdef HAS_MIPS_PREFETCH
1.120 + "pref 30, 128(%[dst]) \n" // set dest, addr 128
1.121 +#endif
1.122 + "$skip_pref30_128: \n"
1.123 + "lw $t2, 40(%[src]) \n"
1.124 + "lw $t3, 44(%[src]) \n"
1.125 + "lw $t4, 48(%[src]) \n"
1.126 + "lw $t5, 52(%[src]) \n"
1.127 + "lw $t6, 56(%[src]) \n"
1.128 + "lw $t7, 60(%[src]) \n"
1.129 +#ifdef HAS_MIPS_PREFETCH
1.130 + "pref 0, 160(%[src]) \n"
1.131 +#endif
1.132 + // bring the next lines of src, addr 160
1.133 + "sw $t0, 32(%[dst]) \n"
1.134 + "sw $t1, 36(%[dst]) \n"
1.135 + "sw $t2, 40(%[dst]) \n"
1.136 + "sw $t3, 44(%[dst]) \n"
1.137 + "sw $t4, 48(%[dst]) \n"
1.138 + "sw $t5, 52(%[dst]) \n"
1.139 + "sw $t6, 56(%[dst]) \n"
1.140 + "sw $t7, 60(%[dst]) \n"
1.141 +
1.142 + "addiu %[dst], %[dst], 64 \n" // adding 64 to dest
1.143 + "sgtu $v1, %[dst], $t9 \n"
1.144 + "bne %[dst], $a3, $loop16w \n"
1.145 + " addiu %[src], %[src], 64 \n" // adding 64 to src
1.146 + "move %[count], $t8 \n"
1.147 +
1.148 + // Here we have src and dest word-aligned but less than 64-bytes to go
1.149 +
1.150 + "chk8w: \n"
1.151 +#ifdef HAS_MIPS_PREFETCH
1.152 + "pref 0, 0x0(%[src]) \n"
1.153 +#endif
1.154 + "andi $t8, %[count], 0x1f \n" // 32-byte chunk?
1.155 + // the t8 is the reminder count past 32-bytes
1.156 + "beq %[count], $t8, chk1w \n"
1.157 + // count=t8,no 32-byte chunk
1.158 + " nop \n"
1.159 +
1.160 + "lw $t0, 0(%[src]) \n"
1.161 + "lw $t1, 4(%[src]) \n"
1.162 + "lw $t2, 8(%[src]) \n"
1.163 + "lw $t3, 12(%[src]) \n"
1.164 + "lw $t4, 16(%[src]) \n"
1.165 + "lw $t5, 20(%[src]) \n"
1.166 + "lw $t6, 24(%[src]) \n"
1.167 + "lw $t7, 28(%[src]) \n"
1.168 + "addiu %[src], %[src], 32 \n"
1.169 +
1.170 + "sw $t0, 0(%[dst]) \n"
1.171 + "sw $t1, 4(%[dst]) \n"
1.172 + "sw $t2, 8(%[dst]) \n"
1.173 + "sw $t3, 12(%[dst]) \n"
1.174 + "sw $t4, 16(%[dst]) \n"
1.175 + "sw $t5, 20(%[dst]) \n"
1.176 + "sw $t6, 24(%[dst]) \n"
1.177 + "sw $t7, 28(%[dst]) \n"
1.178 + "addiu %[dst], %[dst], 32 \n"
1.179 +
1.180 + "chk1w: \n"
1.181 + "andi %[count], $t8, 0x3 \n"
1.182 + // now count is the reminder past 1w chunks
1.183 + "beq %[count], $t8, $last8 \n"
1.184 + " subu $a3, $t8, %[count] \n"
1.185 + // a3 is count of bytes in 1w chunks
1.186 + "addu $a3, %[dst], $a3 \n"
1.187 + // now a3 is the dst address past the 1w chunks
1.188 + // copying in words (4-byte chunks)
1.189 + "$wordCopy_loop: \n"
1.190 + "lw $t3, 0(%[src]) \n"
1.191 + // the first t3 may be equal t0 ... optimize?
1.192 + "addiu %[src], %[src],4 \n"
1.193 + "addiu %[dst], %[dst],4 \n"
1.194 + "bne %[dst], $a3,$wordCopy_loop \n"
1.195 + " sw $t3, -4(%[dst]) \n"
1.196 +
1.197 + // For the last (<8) bytes
1.198 + "$last8: \n"
1.199 + "blez %[count], leave \n"
1.200 + " addu $a3, %[dst], %[count] \n" // a3 -last dst address
1.201 + "$last8loop: \n"
1.202 + "lb $v1, 0(%[src]) \n"
1.203 + "addiu %[src], %[src], 1 \n"
1.204 + "addiu %[dst], %[dst], 1 \n"
1.205 + "bne %[dst], $a3, $last8loop \n"
1.206 + " sb $v1, -1(%[dst]) \n"
1.207 +
1.208 + "leave: \n"
1.209 + " j $ra \n"
1.210 + " nop \n"
1.211 +
1.212 + //
1.213 + // UNALIGNED case
1.214 + //
1.215 +
1.216 + "unaligned: \n"
1.217 + // got here with a3="negu a1"
1.218 + "andi $a3, $a3, 0x3 \n" // a1 is word aligned?
1.219 + "beqz $a3, $ua_chk16w \n"
1.220 + " subu %[count], %[count], $a3 \n"
1.221 + // bytes left after initial a3 bytes
1.222 + "lwr $v1, 0(%[src]) \n"
1.223 + "lwl $v1, 3(%[src]) \n"
1.224 + "addu %[src], %[src], $a3 \n" // a3 may be 1, 2 or 3
1.225 + "swr $v1, 0(%[dst]) \n"
1.226 + "addu %[dst], %[dst], $a3 \n"
1.227 + // below the dst will be word aligned (NOTE1)
1.228 + "$ua_chk16w: \n"
1.229 + "andi $t8, %[count], 0x3f \n" // whole 64-B chunks?
1.230 + // t8 is the byte count after 64-byte chunks
1.231 + "beq %[count], $t8, ua_chk8w \n"
1.232 + // if a2==t8, no 64-byte chunks
1.233 + // There will be at most 1 32-byte chunk after it
1.234 + "subu $a3, %[count], $t8 \n" // the reminder
1.235 + // Here a3 counts bytes in 16w chunks
1.236 + "addu $a3, %[dst], $a3 \n"
1.237 + // Now a3 is the final dst after 64-byte chunks
1.238 + "addu $t0, %[dst], %[count] \n" // t0 "past the end"
1.239 + "subu $t9, $t0, 160 \n"
1.240 + // t9 is the "last safe pref 30,128(a1)" address
1.241 +#ifdef HAS_MIPS_PREFETCH
1.242 + "pref 0, 0(%[src]) \n" // first line of src
1.243 + "pref 0, 32(%[src]) \n" // second line addr 32
1.244 + "pref 0, 64(%[src]) \n"
1.245 + "pref 30, 32(%[dst]) \n"
1.246 +#endif
1.247 + // safe, as we have at least 64 bytes ahead
1.248 + // In case the a1 > t9 don't use "pref 30" at all
1.249 + "sgtu $v1, %[dst], $t9 \n"
1.250 + "bgtz $v1, $ua_loop16w \n"
1.251 + // skip "pref 30,64(a1)" for too short arrays
1.252 + " nop \n"
1.253 + // otherwise, start with using pref30
1.254 +#ifdef HAS_MIPS_PREFETCH
1.255 + "pref 30, 64(%[dst]) \n"
1.256 +#endif
1.257 + "$ua_loop16w: \n"
1.258 +#ifdef HAS_MIPS_PREFETCH
1.259 + "pref 0, 96(%[src]) \n"
1.260 +#endif
1.261 + "lwr $t0, 0(%[src]) \n"
1.262 + "lwl $t0, 3(%[src]) \n"
1.263 + "lwr $t1, 4(%[src]) \n"
1.264 + "bgtz $v1, $ua_skip_pref30_96 \n"
1.265 + " lwl $t1, 7(%[src]) \n"
1.266 +#ifdef HAS_MIPS_PREFETCH
1.267 + "pref 30, 96(%[dst]) \n"
1.268 +#endif
1.269 + // continue setting up the dest, addr 96
1.270 + "$ua_skip_pref30_96: \n"
1.271 + "lwr $t2, 8(%[src]) \n"
1.272 + "lwl $t2, 11(%[src]) \n"
1.273 + "lwr $t3, 12(%[src]) \n"
1.274 + "lwl $t3, 15(%[src]) \n"
1.275 + "lwr $t4, 16(%[src]) \n"
1.276 + "lwl $t4, 19(%[src]) \n"
1.277 + "lwr $t5, 20(%[src]) \n"
1.278 + "lwl $t5, 23(%[src]) \n"
1.279 + "lwr $t6, 24(%[src]) \n"
1.280 + "lwl $t6, 27(%[src]) \n"
1.281 + "lwr $t7, 28(%[src]) \n"
1.282 + "lwl $t7, 31(%[src]) \n"
1.283 +#ifdef HAS_MIPS_PREFETCH
1.284 + "pref 0, 128(%[src]) \n"
1.285 +#endif
1.286 + // bring the next lines of src, addr 128
1.287 + "sw $t0, 0(%[dst]) \n"
1.288 + "sw $t1, 4(%[dst]) \n"
1.289 + "sw $t2, 8(%[dst]) \n"
1.290 + "sw $t3, 12(%[dst]) \n"
1.291 + "sw $t4, 16(%[dst]) \n"
1.292 + "sw $t5, 20(%[dst]) \n"
1.293 + "sw $t6, 24(%[dst]) \n"
1.294 + "sw $t7, 28(%[dst]) \n"
1.295 + "lwr $t0, 32(%[src]) \n"
1.296 + "lwl $t0, 35(%[src]) \n"
1.297 + "lwr $t1, 36(%[src]) \n"
1.298 + "bgtz $v1, ua_skip_pref30_128 \n"
1.299 + " lwl $t1, 39(%[src]) \n"
1.300 +#ifdef HAS_MIPS_PREFETCH
1.301 + "pref 30, 128(%[dst]) \n"
1.302 +#endif
1.303 + // continue setting up the dest, addr 128
1.304 + "ua_skip_pref30_128: \n"
1.305 +
1.306 + "lwr $t2, 40(%[src]) \n"
1.307 + "lwl $t2, 43(%[src]) \n"
1.308 + "lwr $t3, 44(%[src]) \n"
1.309 + "lwl $t3, 47(%[src]) \n"
1.310 + "lwr $t4, 48(%[src]) \n"
1.311 + "lwl $t4, 51(%[src]) \n"
1.312 + "lwr $t5, 52(%[src]) \n"
1.313 + "lwl $t5, 55(%[src]) \n"
1.314 + "lwr $t6, 56(%[src]) \n"
1.315 + "lwl $t6, 59(%[src]) \n"
1.316 + "lwr $t7, 60(%[src]) \n"
1.317 + "lwl $t7, 63(%[src]) \n"
1.318 +#ifdef HAS_MIPS_PREFETCH
1.319 + "pref 0, 160(%[src]) \n"
1.320 +#endif
1.321 + // bring the next lines of src, addr 160
1.322 + "sw $t0, 32(%[dst]) \n"
1.323 + "sw $t1, 36(%[dst]) \n"
1.324 + "sw $t2, 40(%[dst]) \n"
1.325 + "sw $t3, 44(%[dst]) \n"
1.326 + "sw $t4, 48(%[dst]) \n"
1.327 + "sw $t5, 52(%[dst]) \n"
1.328 + "sw $t6, 56(%[dst]) \n"
1.329 + "sw $t7, 60(%[dst]) \n"
1.330 +
1.331 + "addiu %[dst],%[dst],64 \n" // adding 64 to dest
1.332 + "sgtu $v1,%[dst],$t9 \n"
1.333 + "bne %[dst],$a3,$ua_loop16w \n"
1.334 + " addiu %[src],%[src],64 \n" // adding 64 to src
1.335 + "move %[count],$t8 \n"
1.336 +
1.337 + // Here we have src and dest word-aligned but less than 64-bytes to go
1.338 +
1.339 + "ua_chk8w: \n"
1.340 +#ifdef HAS_MIPS_PREFETCH
1.341 + "pref 0, 0x0(%[src]) \n"
1.342 +#endif
1.343 + "andi $t8, %[count], 0x1f \n" // 32-byte chunk?
1.344 + // the t8 is the reminder count
1.345 + "beq %[count], $t8, $ua_chk1w \n"
1.346 + // when count==t8, no 32-byte chunk
1.347 +
1.348 + "lwr $t0, 0(%[src]) \n"
1.349 + "lwl $t0, 3(%[src]) \n"
1.350 + "lwr $t1, 4(%[src]) \n"
1.351 + "lwl $t1, 7(%[src]) \n"
1.352 + "lwr $t2, 8(%[src]) \n"
1.353 + "lwl $t2, 11(%[src]) \n"
1.354 + "lwr $t3, 12(%[src]) \n"
1.355 + "lwl $t3, 15(%[src]) \n"
1.356 + "lwr $t4, 16(%[src]) \n"
1.357 + "lwl $t4, 19(%[src]) \n"
1.358 + "lwr $t5, 20(%[src]) \n"
1.359 + "lwl $t5, 23(%[src]) \n"
1.360 + "lwr $t6, 24(%[src]) \n"
1.361 + "lwl $t6, 27(%[src]) \n"
1.362 + "lwr $t7, 28(%[src]) \n"
1.363 + "lwl $t7, 31(%[src]) \n"
1.364 + "addiu %[src], %[src], 32 \n"
1.365 +
1.366 + "sw $t0, 0(%[dst]) \n"
1.367 + "sw $t1, 4(%[dst]) \n"
1.368 + "sw $t2, 8(%[dst]) \n"
1.369 + "sw $t3, 12(%[dst]) \n"
1.370 + "sw $t4, 16(%[dst]) \n"
1.371 + "sw $t5, 20(%[dst]) \n"
1.372 + "sw $t6, 24(%[dst]) \n"
1.373 + "sw $t7, 28(%[dst]) \n"
1.374 + "addiu %[dst], %[dst], 32 \n"
1.375 +
1.376 + "$ua_chk1w: \n"
1.377 + "andi %[count], $t8, 0x3 \n"
1.378 + // now count is the reminder past 1w chunks
1.379 + "beq %[count], $t8, ua_smallCopy \n"
1.380 + "subu $a3, $t8, %[count] \n"
1.381 + // a3 is count of bytes in 1w chunks
1.382 + "addu $a3, %[dst], $a3 \n"
1.383 + // now a3 is the dst address past the 1w chunks
1.384 +
1.385 + // copying in words (4-byte chunks)
1.386 + "$ua_wordCopy_loop: \n"
1.387 + "lwr $v1, 0(%[src]) \n"
1.388 + "lwl $v1, 3(%[src]) \n"
1.389 + "addiu %[src], %[src], 4 \n"
1.390 + "addiu %[dst], %[dst], 4 \n"
1.391 + // note: dst=a1 is word aligned here, see NOTE1
1.392 + "bne %[dst], $a3, $ua_wordCopy_loop \n"
1.393 + " sw $v1,-4(%[dst]) \n"
1.394 +
1.395 + // Now less than 4 bytes (value in count) left to copy
1.396 + "ua_smallCopy: \n"
1.397 + "beqz %[count], leave \n"
1.398 + " addu $a3, %[dst], %[count] \n" // a3 = last dst address
1.399 + "$ua_smallCopy_loop: \n"
1.400 + "lb $v1, 0(%[src]) \n"
1.401 + "addiu %[src], %[src], 1 \n"
1.402 + "addiu %[dst], %[dst], 1 \n"
1.403 + "bne %[dst],$a3,$ua_smallCopy_loop \n"
1.404 + " sb $v1, -1(%[dst]) \n"
1.405 +
1.406 + "j $ra \n"
1.407 + " nop \n"
1.408 + ".set at \n"
1.409 + ".set reorder \n"
1.410 + : [dst] "+r" (dst), [src] "+r" (src)
1.411 + : [count] "r" (count)
1.412 + : "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1.413 + "t8", "t9", "a3", "v1", "at"
1.414 + );
1.415 +}
1.416 +#endif // HAS_COPYROW_MIPS
1.417 +
1.418 +// MIPS DSPR2 functions
1.419 +#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips_dsp) && \
1.420 + (__mips_dsp_rev >= 2)
1.421 +void SplitUVRow_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
1.422 + int width) {
1.423 + __asm__ __volatile__ (
1.424 + ".set push \n"
1.425 + ".set noreorder \n"
1.426 + "srl $t4, %[width], 4 \n" // multiplies of 16
1.427 + "blez $t4, 2f \n"
1.428 + " andi %[width], %[width], 0xf \n" // residual
1.429 +
1.430 + ".p2align 2 \n"
1.431 + "1: \n"
1.432 + "addiu $t4, $t4, -1 \n"
1.433 + "lw $t0, 0(%[src_uv]) \n" // V1 | U1 | V0 | U0
1.434 + "lw $t1, 4(%[src_uv]) \n" // V3 | U3 | V2 | U2
1.435 + "lw $t2, 8(%[src_uv]) \n" // V5 | U5 | V4 | U4
1.436 + "lw $t3, 12(%[src_uv]) \n" // V7 | U7 | V6 | U6
1.437 + "lw $t5, 16(%[src_uv]) \n" // V9 | U9 | V8 | U8
1.438 + "lw $t6, 20(%[src_uv]) \n" // V11 | U11 | V10 | U10
1.439 + "lw $t7, 24(%[src_uv]) \n" // V13 | U13 | V12 | U12
1.440 + "lw $t8, 28(%[src_uv]) \n" // V15 | U15 | V14 | U14
1.441 + "addiu %[src_uv], %[src_uv], 32 \n"
1.442 + "precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
1.443 + "precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
1.444 + "precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
1.445 + "precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
1.446 + "precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
1.447 + "precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
1.448 + "precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
1.449 + "precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
1.450 + "sw $t9, 0(%[dst_v]) \n"
1.451 + "sw $t0, 0(%[dst_u]) \n"
1.452 + "sw $t1, 4(%[dst_v]) \n"
1.453 + "sw $t2, 4(%[dst_u]) \n"
1.454 + "sw $t3, 8(%[dst_v]) \n"
1.455 + "sw $t5, 8(%[dst_u]) \n"
1.456 + "sw $t6, 12(%[dst_v]) \n"
1.457 + "sw $t7, 12(%[dst_u]) \n"
1.458 + "addiu %[dst_v], %[dst_v], 16 \n"
1.459 + "bgtz $t4, 1b \n"
1.460 + " addiu %[dst_u], %[dst_u], 16 \n"
1.461 +
1.462 + "beqz %[width], 3f \n"
1.463 + " nop \n"
1.464 +
1.465 + "2: \n"
1.466 + "lbu $t0, 0(%[src_uv]) \n"
1.467 + "lbu $t1, 1(%[src_uv]) \n"
1.468 + "addiu %[src_uv], %[src_uv], 2 \n"
1.469 + "addiu %[width], %[width], -1 \n"
1.470 + "sb $t0, 0(%[dst_u]) \n"
1.471 + "sb $t1, 0(%[dst_v]) \n"
1.472 + "addiu %[dst_u], %[dst_u], 1 \n"
1.473 + "bgtz %[width], 2b \n"
1.474 + " addiu %[dst_v], %[dst_v], 1 \n"
1.475 +
1.476 + "3: \n"
1.477 + ".set pop \n"
1.478 + : [src_uv] "+r" (src_uv),
1.479 + [width] "+r" (width),
1.480 + [dst_u] "+r" (dst_u),
1.481 + [dst_v] "+r" (dst_v)
1.482 + :
1.483 + : "t0", "t1", "t2", "t3",
1.484 + "t4", "t5", "t6", "t7", "t8", "t9"
1.485 + );
1.486 +}
1.487 +
1.488 +void SplitUVRow_Unaligned_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u,
1.489 + uint8* dst_v, int width) {
1.490 + __asm__ __volatile__ (
1.491 + ".set push \n"
1.492 + ".set noreorder \n"
1.493 + "srl $t4, %[width], 4 \n" // multiplies of 16
1.494 + "blez $t4, 2f \n"
1.495 + " andi %[width], %[width], 0xf \n" // residual
1.496 +
1.497 + ".p2align 2 \n"
1.498 + "1: \n"
1.499 + "addiu $t4, $t4, -1 \n"
1.500 + "lwr $t0, 0(%[src_uv]) \n"
1.501 + "lwl $t0, 3(%[src_uv]) \n" // V1 | U1 | V0 | U0
1.502 + "lwr $t1, 4(%[src_uv]) \n"
1.503 + "lwl $t1, 7(%[src_uv]) \n" // V3 | U3 | V2 | U2
1.504 + "lwr $t2, 8(%[src_uv]) \n"
1.505 + "lwl $t2, 11(%[src_uv]) \n" // V5 | U5 | V4 | U4
1.506 + "lwr $t3, 12(%[src_uv]) \n"
1.507 + "lwl $t3, 15(%[src_uv]) \n" // V7 | U7 | V6 | U6
1.508 + "lwr $t5, 16(%[src_uv]) \n"
1.509 + "lwl $t5, 19(%[src_uv]) \n" // V9 | U9 | V8 | U8
1.510 + "lwr $t6, 20(%[src_uv]) \n"
1.511 + "lwl $t6, 23(%[src_uv]) \n" // V11 | U11 | V10 | U10
1.512 + "lwr $t7, 24(%[src_uv]) \n"
1.513 + "lwl $t7, 27(%[src_uv]) \n" // V13 | U13 | V12 | U12
1.514 + "lwr $t8, 28(%[src_uv]) \n"
1.515 + "lwl $t8, 31(%[src_uv]) \n" // V15 | U15 | V14 | U14
1.516 + "precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
1.517 + "precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
1.518 + "precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
1.519 + "precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
1.520 + "precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
1.521 + "precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
1.522 + "precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
1.523 + "precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
1.524 + "addiu %[src_uv], %[src_uv], 32 \n"
1.525 + "swr $t9, 0(%[dst_v]) \n"
1.526 + "swl $t9, 3(%[dst_v]) \n"
1.527 + "swr $t0, 0(%[dst_u]) \n"
1.528 + "swl $t0, 3(%[dst_u]) \n"
1.529 + "swr $t1, 4(%[dst_v]) \n"
1.530 + "swl $t1, 7(%[dst_v]) \n"
1.531 + "swr $t2, 4(%[dst_u]) \n"
1.532 + "swl $t2, 7(%[dst_u]) \n"
1.533 + "swr $t3, 8(%[dst_v]) \n"
1.534 + "swl $t3, 11(%[dst_v]) \n"
1.535 + "swr $t5, 8(%[dst_u]) \n"
1.536 + "swl $t5, 11(%[dst_u]) \n"
1.537 + "swr $t6, 12(%[dst_v]) \n"
1.538 + "swl $t6, 15(%[dst_v]) \n"
1.539 + "swr $t7, 12(%[dst_u]) \n"
1.540 + "swl $t7, 15(%[dst_u]) \n"
1.541 + "addiu %[dst_u], %[dst_u], 16 \n"
1.542 + "bgtz $t4, 1b \n"
1.543 + " addiu %[dst_v], %[dst_v], 16 \n"
1.544 +
1.545 + "beqz %[width], 3f \n"
1.546 + " nop \n"
1.547 +
1.548 + "2: \n"
1.549 + "lbu $t0, 0(%[src_uv]) \n"
1.550 + "lbu $t1, 1(%[src_uv]) \n"
1.551 + "addiu %[src_uv], %[src_uv], 2 \n"
1.552 + "addiu %[width], %[width], -1 \n"
1.553 + "sb $t0, 0(%[dst_u]) \n"
1.554 + "sb $t1, 0(%[dst_v]) \n"
1.555 + "addiu %[dst_u], %[dst_u], 1 \n"
1.556 + "bgtz %[width], 2b \n"
1.557 + " addiu %[dst_v], %[dst_v], 1 \n"
1.558 +
1.559 + "3: \n"
1.560 + ".set pop \n"
1.561 + : [src_uv] "+r" (src_uv),
1.562 + [width] "+r" (width),
1.563 + [dst_u] "+r" (dst_u),
1.564 + [dst_v] "+r" (dst_v)
1.565 + :
1.566 + : "t0", "t1", "t2", "t3",
1.567 + "t4", "t5", "t6", "t7", "t8", "t9"
1.568 + );
1.569 +}
1.570 +
1.571 +void MirrorRow_MIPS_DSPR2(const uint8* src, uint8* dst, int width) {
1.572 + __asm__ __volatile__ (
1.573 + ".set push \n"
1.574 + ".set noreorder \n"
1.575 +
1.576 + "srl $t4, %[width], 4 \n" // multiplies of 16
1.577 + "andi $t5, %[width], 0xf \n"
1.578 + "blez $t4, 2f \n"
1.579 + " addu %[src], %[src], %[width] \n" // src += width
1.580 +
1.581 + ".p2align 2 \n"
1.582 + "1: \n"
1.583 + "lw $t0, -16(%[src]) \n" // |3|2|1|0|
1.584 + "lw $t1, -12(%[src]) \n" // |7|6|5|4|
1.585 + "lw $t2, -8(%[src]) \n" // |11|10|9|8|
1.586 + "lw $t3, -4(%[src]) \n" // |15|14|13|12|
1.587 + "wsbh $t0, $t0 \n" // |2|3|0|1|
1.588 + "wsbh $t1, $t1 \n" // |6|7|4|5|
1.589 + "wsbh $t2, $t2 \n" // |10|11|8|9|
1.590 + "wsbh $t3, $t3 \n" // |14|15|12|13|
1.591 + "rotr $t0, $t0, 16 \n" // |0|1|2|3|
1.592 + "rotr $t1, $t1, 16 \n" // |4|5|6|7|
1.593 + "rotr $t2, $t2, 16 \n" // |8|9|10|11|
1.594 + "rotr $t3, $t3, 16 \n" // |12|13|14|15|
1.595 + "addiu %[src], %[src], -16 \n"
1.596 + "addiu $t4, $t4, -1 \n"
1.597 + "sw $t3, 0(%[dst]) \n" // |15|14|13|12|
1.598 + "sw $t2, 4(%[dst]) \n" // |11|10|9|8|
1.599 + "sw $t1, 8(%[dst]) \n" // |7|6|5|4|
1.600 + "sw $t0, 12(%[dst]) \n" // |3|2|1|0|
1.601 + "bgtz $t4, 1b \n"
1.602 + " addiu %[dst], %[dst], 16 \n"
1.603 + "beqz $t5, 3f \n"
1.604 + " nop \n"
1.605 +
1.606 + "2: \n"
1.607 + "lbu $t0, -1(%[src]) \n"
1.608 + "addiu $t5, $t5, -1 \n"
1.609 + "addiu %[src], %[src], -1 \n"
1.610 + "sb $t0, 0(%[dst]) \n"
1.611 + "bgez $t5, 2b \n"
1.612 + " addiu %[dst], %[dst], 1 \n"
1.613 +
1.614 + "3: \n"
1.615 + ".set pop \n"
1.616 + : [src] "+r" (src), [dst] "+r" (dst)
1.617 + : [width] "r" (width)
1.618 + : "t0", "t1", "t2", "t3", "t4", "t5"
1.619 + );
1.620 +}
1.621 +
1.622 +void MirrorUVRow_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
1.623 + int width) {
1.624 + int x = 0;
1.625 + int y = 0;
1.626 + __asm__ __volatile__ (
1.627 + ".set push \n"
1.628 + ".set noreorder \n"
1.629 +
1.630 + "addu $t4, %[width], %[width] \n"
1.631 + "srl %[x], %[width], 4 \n"
1.632 + "andi %[y], %[width], 0xf \n"
1.633 + "blez %[x], 2f \n"
1.634 + " addu %[src_uv], %[src_uv], $t4 \n"
1.635 +
1.636 + ".p2align 2 \n"
1.637 + "1: \n"
1.638 + "lw $t0, -32(%[src_uv]) \n" // |3|2|1|0|
1.639 + "lw $t1, -28(%[src_uv]) \n" // |7|6|5|4|
1.640 + "lw $t2, -24(%[src_uv]) \n" // |11|10|9|8|
1.641 + "lw $t3, -20(%[src_uv]) \n" // |15|14|13|12|
1.642 + "lw $t4, -16(%[src_uv]) \n" // |19|18|17|16|
1.643 + "lw $t6, -12(%[src_uv]) \n" // |23|22|21|20|
1.644 + "lw $t7, -8(%[src_uv]) \n" // |27|26|25|24|
1.645 + "lw $t8, -4(%[src_uv]) \n" // |31|30|29|28|
1.646 +
1.647 + "rotr $t0, $t0, 16 \n" // |1|0|3|2|
1.648 + "rotr $t1, $t1, 16 \n" // |5|4|7|6|
1.649 + "rotr $t2, $t2, 16 \n" // |9|8|11|10|
1.650 + "rotr $t3, $t3, 16 \n" // |13|12|15|14|
1.651 + "rotr $t4, $t4, 16 \n" // |17|16|19|18|
1.652 + "rotr $t6, $t6, 16 \n" // |21|20|23|22|
1.653 + "rotr $t7, $t7, 16 \n" // |25|24|27|26|
1.654 + "rotr $t8, $t8, 16 \n" // |29|28|31|30|
1.655 + "precr.qb.ph $t9, $t0, $t1 \n" // |0|2|4|6|
1.656 + "precrq.qb.ph $t5, $t0, $t1 \n" // |1|3|5|7|
1.657 + "precr.qb.ph $t0, $t2, $t3 \n" // |8|10|12|14|
1.658 + "precrq.qb.ph $t1, $t2, $t3 \n" // |9|11|13|15|
1.659 + "precr.qb.ph $t2, $t4, $t6 \n" // |16|18|20|22|
1.660 + "precrq.qb.ph $t3, $t4, $t6 \n" // |17|19|21|23|
1.661 + "precr.qb.ph $t4, $t7, $t8 \n" // |24|26|28|30|
1.662 + "precrq.qb.ph $t6, $t7, $t8 \n" // |25|27|29|31|
1.663 + "addiu %[src_uv], %[src_uv], -32 \n"
1.664 + "addiu %[x], %[x], -1 \n"
1.665 + "swr $t4, 0(%[dst_u]) \n"
1.666 + "swl $t4, 3(%[dst_u]) \n" // |30|28|26|24|
1.667 + "swr $t6, 0(%[dst_v]) \n"
1.668 + "swl $t6, 3(%[dst_v]) \n" // |31|29|27|25|
1.669 + "swr $t2, 4(%[dst_u]) \n"
1.670 + "swl $t2, 7(%[dst_u]) \n" // |22|20|18|16|
1.671 + "swr $t3, 4(%[dst_v]) \n"
1.672 + "swl $t3, 7(%[dst_v]) \n" // |23|21|19|17|
1.673 + "swr $t0, 8(%[dst_u]) \n"
1.674 + "swl $t0, 11(%[dst_u]) \n" // |14|12|10|8|
1.675 + "swr $t1, 8(%[dst_v]) \n"
1.676 + "swl $t1, 11(%[dst_v]) \n" // |15|13|11|9|
1.677 + "swr $t9, 12(%[dst_u]) \n"
1.678 + "swl $t9, 15(%[dst_u]) \n" // |6|4|2|0|
1.679 + "swr $t5, 12(%[dst_v]) \n"
1.680 + "swl $t5, 15(%[dst_v]) \n" // |7|5|3|1|
1.681 + "addiu %[dst_v], %[dst_v], 16 \n"
1.682 + "bgtz %[x], 1b \n"
1.683 + " addiu %[dst_u], %[dst_u], 16 \n"
1.684 + "beqz %[y], 3f \n"
1.685 + " nop \n"
1.686 + "b 2f \n"
1.687 + " nop \n"
1.688 +
1.689 + "2: \n"
1.690 + "lbu $t0, -2(%[src_uv]) \n"
1.691 + "lbu $t1, -1(%[src_uv]) \n"
1.692 + "addiu %[src_uv], %[src_uv], -2 \n"
1.693 + "addiu %[y], %[y], -1 \n"
1.694 + "sb $t0, 0(%[dst_u]) \n"
1.695 + "sb $t1, 0(%[dst_v]) \n"
1.696 + "addiu %[dst_u], %[dst_u], 1 \n"
1.697 + "bgtz %[y], 2b \n"
1.698 + " addiu %[dst_v], %[dst_v], 1 \n"
1.699 +
1.700 + "3: \n"
1.701 + ".set pop \n"
1.702 + : [src_uv] "+r" (src_uv),
1.703 + [dst_u] "+r" (dst_u),
1.704 + [dst_v] "+r" (dst_v),
1.705 + [x] "=&r" (x),
1.706 + [y] "+r" (y)
1.707 + : [width] "r" (width)
1.708 + : "t0", "t1", "t2", "t3", "t4",
1.709 + "t5", "t7", "t8", "t9"
1.710 + );
1.711 +}
1.712 +
1.713 +// Convert (4 Y and 2 VU) I422 and arrange RGB values into
1.714 +// t5 = | 0 | B0 | 0 | b0 |
1.715 +// t4 = | 0 | B1 | 0 | b1 |
1.716 +// t9 = | 0 | G0 | 0 | g0 |
1.717 +// t8 = | 0 | G1 | 0 | g1 |
1.718 +// t2 = | 0 | R0 | 0 | r0 |
1.719 +// t1 = | 0 | R1 | 0 | r1 |
1.720 +#define I422ToTransientMipsRGB \
1.721 + "lw $t0, 0(%[y_buf]) \n" \
1.722 + "lhu $t1, 0(%[u_buf]) \n" \
1.723 + "lhu $t2, 0(%[v_buf]) \n" \
1.724 + "preceu.ph.qbr $t1, $t1 \n" \
1.725 + "preceu.ph.qbr $t2, $t2 \n" \
1.726 + "preceu.ph.qbra $t3, $t0 \n" \
1.727 + "preceu.ph.qbla $t0, $t0 \n" \
1.728 + "subu.ph $t1, $t1, $s5 \n" \
1.729 + "subu.ph $t2, $t2, $s5 \n" \
1.730 + "subu.ph $t3, $t3, $s4 \n" \
1.731 + "subu.ph $t0, $t0, $s4 \n" \
1.732 + "mul.ph $t3, $t3, $s0 \n" \
1.733 + "mul.ph $t0, $t0, $s0 \n" \
1.734 + "shll.ph $t4, $t1, 0x7 \n" \
1.735 + "subu.ph $t4, $t4, $t1 \n" \
1.736 + "mul.ph $t6, $t1, $s1 \n" \
1.737 + "mul.ph $t1, $t2, $s2 \n" \
1.738 + "addq_s.ph $t5, $t4, $t3 \n" \
1.739 + "addq_s.ph $t4, $t4, $t0 \n" \
1.740 + "shra.ph $t5, $t5, 6 \n" \
1.741 + "shra.ph $t4, $t4, 6 \n" \
1.742 + "addiu %[u_buf], 2 \n" \
1.743 + "addiu %[v_buf], 2 \n" \
1.744 + "addu.ph $t6, $t6, $t1 \n" \
1.745 + "mul.ph $t1, $t2, $s3 \n" \
1.746 + "addu.ph $t9, $t6, $t3 \n" \
1.747 + "addu.ph $t8, $t6, $t0 \n" \
1.748 + "shra.ph $t9, $t9, 6 \n" \
1.749 + "shra.ph $t8, $t8, 6 \n" \
1.750 + "addu.ph $t2, $t1, $t3 \n" \
1.751 + "addu.ph $t1, $t1, $t0 \n" \
1.752 + "shra.ph $t2, $t2, 6 \n" \
1.753 + "shra.ph $t1, $t1, 6 \n" \
1.754 + "subu.ph $t5, $t5, $s5 \n" \
1.755 + "subu.ph $t4, $t4, $s5 \n" \
1.756 + "subu.ph $t9, $t9, $s5 \n" \
1.757 + "subu.ph $t8, $t8, $s5 \n" \
1.758 + "subu.ph $t2, $t2, $s5 \n" \
1.759 + "subu.ph $t1, $t1, $s5 \n" \
1.760 + "shll_s.ph $t5, $t5, 8 \n" \
1.761 + "shll_s.ph $t4, $t4, 8 \n" \
1.762 + "shll_s.ph $t9, $t9, 8 \n" \
1.763 + "shll_s.ph $t8, $t8, 8 \n" \
1.764 + "shll_s.ph $t2, $t2, 8 \n" \
1.765 + "shll_s.ph $t1, $t1, 8 \n" \
1.766 + "shra.ph $t5, $t5, 8 \n" \
1.767 + "shra.ph $t4, $t4, 8 \n" \
1.768 + "shra.ph $t9, $t9, 8 \n" \
1.769 + "shra.ph $t8, $t8, 8 \n" \
1.770 + "shra.ph $t2, $t2, 8 \n" \
1.771 + "shra.ph $t1, $t1, 8 \n" \
1.772 + "addu.ph $t5, $t5, $s5 \n" \
1.773 + "addu.ph $t4, $t4, $s5 \n" \
1.774 + "addu.ph $t9, $t9, $s5 \n" \
1.775 + "addu.ph $t8, $t8, $s5 \n" \
1.776 + "addu.ph $t2, $t2, $s5 \n" \
1.777 + "addu.ph $t1, $t1, $s5 \n"
1.778 +
1.779 +void I422ToARGBRow_MIPS_DSPR2(const uint8* y_buf,
1.780 + const uint8* u_buf,
1.781 + const uint8* v_buf,
1.782 + uint8* rgb_buf,
1.783 + int width) {
1.784 + __asm__ __volatile__ (
1.785 + ".set push \n"
1.786 + ".set noreorder \n"
1.787 + "beqz %[width], 2f \n"
1.788 + " repl.ph $s0, 74 \n" // |YG|YG| = |74|74|
1.789 + "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
1.790 + "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
1.791 + "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
1.792 + "repl.ph $s4, 16 \n" // |0|16|0|16|
1.793 + "repl.ph $s5, 128 \n" // |128|128| // clipping
1.794 + "lui $s6, 0xff00 \n"
1.795 + "ori $s6, 0xff00 \n" // |ff|00|ff|00|ff|
1.796 +
1.797 + ".p2align 2 \n"
1.798 + "1: \n"
1.799 + I422ToTransientMipsRGB
1.800 +// Arranging into argb format
1.801 + "precr.qb.ph $t4, $t8, $t4 \n" // |G1|g1|B1|b1|
1.802 + "precr.qb.ph $t5, $t9, $t5 \n" // |G0|g0|B0|b0|
1.803 + "addiu %[width], -4 \n"
1.804 + "precrq.qb.ph $t8, $t4, $t5 \n" // |G1|B1|G0|B0|
1.805 + "precr.qb.ph $t9, $t4, $t5 \n" // |g1|b1|g0|b0|
1.806 + "precr.qb.ph $t2, $t1, $t2 \n" // |R1|r1|R0|r0|
1.807 +
1.808 + "addiu %[y_buf], 4 \n"
1.809 + "preceu.ph.qbla $t1, $t2 \n" // |0 |R1|0 |R0|
1.810 + "preceu.ph.qbra $t2, $t2 \n" // |0 |r1|0 |r0|
1.811 + "or $t1, $t1, $s6 \n" // |ff|R1|ff|R0|
1.812 + "or $t2, $t2, $s6 \n" // |ff|r1|ff|r0|
1.813 + "precrq.ph.w $t0, $t2, $t9 \n" // |ff|r1|g1|b1|
1.814 + "precrq.ph.w $t3, $t1, $t8 \n" // |ff|R1|G1|B1|
1.815 + "sll $t9, $t9, 16 \n"
1.816 + "sll $t8, $t8, 16 \n"
1.817 + "packrl.ph $t2, $t2, $t9 \n" // |ff|r0|g0|b0|
1.818 + "packrl.ph $t1, $t1, $t8 \n" // |ff|R0|G0|B0|
1.819 +// Store results.
1.820 + "sw $t2, 0(%[rgb_buf]) \n"
1.821 + "sw $t0, 4(%[rgb_buf]) \n"
1.822 + "sw $t1, 8(%[rgb_buf]) \n"
1.823 + "sw $t3, 12(%[rgb_buf]) \n"
1.824 + "bnez %[width], 1b \n"
1.825 + " addiu %[rgb_buf], 16 \n"
1.826 + "2: \n"
1.827 + ".set pop \n"
1.828 + :[y_buf] "+r" (y_buf),
1.829 + [u_buf] "+r" (u_buf),
1.830 + [v_buf] "+r" (v_buf),
1.831 + [width] "+r" (width),
1.832 + [rgb_buf] "+r" (rgb_buf)
1.833 + :
1.834 + : "t0", "t1", "t2", "t3", "t4", "t5",
1.835 + "t6", "t7", "t8", "t9",
1.836 + "s0", "s1", "s2", "s3",
1.837 + "s4", "s5", "s6"
1.838 + );
1.839 +}
1.840 +
1.841 +void I422ToABGRRow_MIPS_DSPR2(const uint8* y_buf,
1.842 + const uint8* u_buf,
1.843 + const uint8* v_buf,
1.844 + uint8* rgb_buf,
1.845 + int width) {
1.846 + __asm__ __volatile__ (
1.847 + ".set push \n"
1.848 + ".set noreorder \n"
1.849 + "beqz %[width], 2f \n"
1.850 + " repl.ph $s0, 74 \n" // |YG|YG| = |74|74|
1.851 + "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
1.852 + "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
1.853 + "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
1.854 + "repl.ph $s4, 16 \n" // |0|16|0|16|
1.855 + "repl.ph $s5, 128 \n" // |128|128|
1.856 + "lui $s6, 0xff00 \n"
1.857 + "ori $s6, 0xff00 \n" // |ff|00|ff|00|
1.858 +
1.859 + ".p2align 2 \n"
1.860 + "1: \n"
1.861 + I422ToTransientMipsRGB
1.862 +// Arranging into abgr format
1.863 + "precr.qb.ph $t0, $t8, $t1 \n" // |G1|g1|R1|r1|
1.864 + "precr.qb.ph $t3, $t9, $t2 \n" // |G0|g0|R0|r0|
1.865 + "precrq.qb.ph $t8, $t0, $t3 \n" // |G1|R1|G0|R0|
1.866 + "precr.qb.ph $t9, $t0, $t3 \n" // |g1|r1|g0|r0|
1.867 +
1.868 + "precr.qb.ph $t2, $t4, $t5 \n" // |B1|b1|B0|b0|
1.869 + "addiu %[width], -4 \n"
1.870 + "addiu %[y_buf], 4 \n"
1.871 + "preceu.ph.qbla $t1, $t2 \n" // |0 |B1|0 |B0|
1.872 + "preceu.ph.qbra $t2, $t2 \n" // |0 |b1|0 |b0|
1.873 + "or $t1, $t1, $s6 \n" // |ff|B1|ff|B0|
1.874 + "or $t2, $t2, $s6 \n" // |ff|b1|ff|b0|
1.875 + "precrq.ph.w $t0, $t2, $t9 \n" // |ff|b1|g1|r1|
1.876 + "precrq.ph.w $t3, $t1, $t8 \n" // |ff|B1|G1|R1|
1.877 + "sll $t9, $t9, 16 \n"
1.878 + "sll $t8, $t8, 16 \n"
1.879 + "packrl.ph $t2, $t2, $t9 \n" // |ff|b0|g0|r0|
1.880 + "packrl.ph $t1, $t1, $t8 \n" // |ff|B0|G0|R0|
1.881 +// Store results.
1.882 + "sw $t2, 0(%[rgb_buf]) \n"
1.883 + "sw $t0, 4(%[rgb_buf]) \n"
1.884 + "sw $t1, 8(%[rgb_buf]) \n"
1.885 + "sw $t3, 12(%[rgb_buf]) \n"
1.886 + "bnez %[width], 1b \n"
1.887 + " addiu %[rgb_buf], 16 \n"
1.888 + "2: \n"
1.889 + ".set pop \n"
1.890 + :[y_buf] "+r" (y_buf),
1.891 + [u_buf] "+r" (u_buf),
1.892 + [v_buf] "+r" (v_buf),
1.893 + [width] "+r" (width),
1.894 + [rgb_buf] "+r" (rgb_buf)
1.895 + :
1.896 + : "t0", "t1", "t2", "t3", "t4", "t5",
1.897 + "t6", "t7", "t8", "t9",
1.898 + "s0", "s1", "s2", "s3",
1.899 + "s4", "s5", "s6"
1.900 + );
1.901 +}
1.902 +
1.903 +void I422ToBGRARow_MIPS_DSPR2(const uint8* y_buf,
1.904 + const uint8* u_buf,
1.905 + const uint8* v_buf,
1.906 + uint8* rgb_buf,
1.907 + int width) {
1.908 + __asm__ __volatile__ (
1.909 + ".set push \n"
1.910 + ".set noreorder \n"
1.911 + "beqz %[width], 2f \n"
1.912 + " repl.ph $s0, 74 \n" // |YG|YG| = |74 |74 |
1.913 + "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
1.914 + "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
1.915 + "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
1.916 + "repl.ph $s4, 16 \n" // |0|16|0|16|
1.917 + "repl.ph $s5, 128 \n" // |128|128|
1.918 + "lui $s6, 0xff \n"
1.919 + "ori $s6, 0xff \n" // |00|ff|00|ff|
1.920 +
1.921 + ".p2align 2 \n"
1.922 + "1: \n"
1.923 + I422ToTransientMipsRGB
1.924 + // Arranging into bgra format
1.925 + "precr.qb.ph $t4, $t4, $t8 \n" // |B1|b1|G1|g1|
1.926 + "precr.qb.ph $t5, $t5, $t9 \n" // |B0|b0|G0|g0|
1.927 + "precrq.qb.ph $t8, $t4, $t5 \n" // |B1|G1|B0|G0|
1.928 + "precr.qb.ph $t9, $t4, $t5 \n" // |b1|g1|b0|g0|
1.929 +
1.930 + "precr.qb.ph $t2, $t1, $t2 \n" // |R1|r1|R0|r0|
1.931 + "addiu %[width], -4 \n"
1.932 + "addiu %[y_buf], 4 \n"
1.933 + "preceu.ph.qbla $t1, $t2 \n" // |0 |R1|0 |R0|
1.934 + "preceu.ph.qbra $t2, $t2 \n" // |0 |r1|0 |r0|
1.935 + "sll $t1, $t1, 8 \n" // |R1|0 |R0|0 |
1.936 + "sll $t2, $t2, 8 \n" // |r1|0 |r0|0 |
1.937 + "or $t1, $t1, $s6 \n" // |R1|ff|R0|ff|
1.938 + "or $t2, $t2, $s6 \n" // |r1|ff|r0|ff|
1.939 + "precrq.ph.w $t0, $t9, $t2 \n" // |b1|g1|r1|ff|
1.940 + "precrq.ph.w $t3, $t8, $t1 \n" // |B1|G1|R1|ff|
1.941 + "sll $t1, $t1, 16 \n"
1.942 + "sll $t2, $t2, 16 \n"
1.943 + "packrl.ph $t2, $t9, $t2 \n" // |b0|g0|r0|ff|
1.944 + "packrl.ph $t1, $t8, $t1 \n" // |B0|G0|R0|ff|
1.945 +// Store results.
1.946 + "sw $t2, 0(%[rgb_buf]) \n"
1.947 + "sw $t0, 4(%[rgb_buf]) \n"
1.948 + "sw $t1, 8(%[rgb_buf]) \n"
1.949 + "sw $t3, 12(%[rgb_buf]) \n"
1.950 + "bnez %[width], 1b \n"
1.951 + " addiu %[rgb_buf], 16 \n"
1.952 + "2: \n"
1.953 + ".set pop \n"
1.954 + :[y_buf] "+r" (y_buf),
1.955 + [u_buf] "+r" (u_buf),
1.956 + [v_buf] "+r" (v_buf),
1.957 + [width] "+r" (width),
1.958 + [rgb_buf] "+r" (rgb_buf)
1.959 + :
1.960 + : "t0", "t1", "t2", "t3", "t4", "t5",
1.961 + "t6", "t7", "t8", "t9",
1.962 + "s0", "s1", "s2", "s3",
1.963 + "s4", "s5", "s6"
1.964 + );
1.965 +}
1.966 +
1.967 +// Bilinear filter 8x2 -> 8x1
1.968 +void InterpolateRows_MIPS_DSPR2(uint8* dst_ptr, const uint8* src_ptr,
1.969 + ptrdiff_t src_stride, int dst_width,
1.970 + int source_y_fraction) {
1.971 + int y0_fraction = 256 - source_y_fraction;
1.972 + const uint8* src_ptr1 = src_ptr + src_stride;
1.973 +
1.974 + __asm__ __volatile__ (
1.975 + ".set push \n"
1.976 + ".set noreorder \n"
1.977 +
1.978 + "replv.ph $t0, %[y0_fraction] \n"
1.979 + "replv.ph $t1, %[source_y_fraction] \n"
1.980 +
1.981 + ".p2align 2 \n"
1.982 + "1: \n"
1.983 + "lw $t2, 0(%[src_ptr]) \n"
1.984 + "lw $t3, 0(%[src_ptr1]) \n"
1.985 + "lw $t4, 4(%[src_ptr]) \n"
1.986 + "lw $t5, 4(%[src_ptr1]) \n"
1.987 + "muleu_s.ph.qbl $t6, $t2, $t0 \n"
1.988 + "muleu_s.ph.qbr $t7, $t2, $t0 \n"
1.989 + "muleu_s.ph.qbl $t8, $t3, $t1 \n"
1.990 + "muleu_s.ph.qbr $t9, $t3, $t1 \n"
1.991 + "muleu_s.ph.qbl $t2, $t4, $t0 \n"
1.992 + "muleu_s.ph.qbr $t3, $t4, $t0 \n"
1.993 + "muleu_s.ph.qbl $t4, $t5, $t1 \n"
1.994 + "muleu_s.ph.qbr $t5, $t5, $t1 \n"
1.995 + "addq.ph $t6, $t6, $t8 \n"
1.996 + "addq.ph $t7, $t7, $t9 \n"
1.997 + "addq.ph $t2, $t2, $t4 \n"
1.998 + "addq.ph $t3, $t3, $t5 \n"
1.999 + "shra.ph $t6, $t6, 8 \n"
1.1000 + "shra.ph $t7, $t7, 8 \n"
1.1001 + "shra.ph $t2, $t2, 8 \n"
1.1002 + "shra.ph $t3, $t3, 8 \n"
1.1003 + "precr.qb.ph $t6, $t6, $t7 \n"
1.1004 + "precr.qb.ph $t2, $t2, $t3 \n"
1.1005 + "addiu %[src_ptr], %[src_ptr], 8 \n"
1.1006 + "addiu %[src_ptr1], %[src_ptr1], 8 \n"
1.1007 + "addiu %[dst_width], %[dst_width], -8 \n"
1.1008 + "sw $t6, 0(%[dst_ptr]) \n"
1.1009 + "sw $t2, 4(%[dst_ptr]) \n"
1.1010 + "bgtz %[dst_width], 1b \n"
1.1011 + " addiu %[dst_ptr], %[dst_ptr], 8 \n"
1.1012 +
1.1013 + ".set pop \n"
1.1014 + : [dst_ptr] "+r" (dst_ptr),
1.1015 + [src_ptr1] "+r" (src_ptr1),
1.1016 + [src_ptr] "+r" (src_ptr),
1.1017 + [dst_width] "+r" (dst_width)
1.1018 + : [source_y_fraction] "r" (source_y_fraction),
1.1019 + [y0_fraction] "r" (y0_fraction),
1.1020 + [src_stride] "r" (src_stride)
1.1021 + : "t0", "t1", "t2", "t3", "t4", "t5",
1.1022 + "t6", "t7", "t8", "t9"
1.1023 + );
1.1024 +}
1.1025 +#endif // __mips_dsp_rev >= 2
1.1026 +
1.1027 +#endif // defined(__mips__)
1.1028 +
1.1029 +#ifdef __cplusplus
1.1030 +} // extern "C"
1.1031 +} // namespace libyuv
1.1032 +#endif
