1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/media/libyuv/util/cpuid.c Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,94 @@
1.4 +/*
1.5 + * Copyright 2012 The LibYuv Project Authors. All rights reserved.
1.6 + *
1.7 + * Use of this source code is governed by a BSD-style license
1.8 + * that can be found in the LICENSE file in the root of the source
1.9 + * tree. An additional intellectual property rights grant can be found
1.10 + * in the file PATENTS. All contributing project authors may
1.11 + * be found in the AUTHORS file in the root of the source tree.
1.12 + */
1.13 +
1.14 +#include <stdio.h>
1.15 +#include <stdlib.h>
1.16 +#include <string.h>
1.17 +
1.18 +#define INCLUDE_LIBYUV_COMPARE_H_
1.19 +#include "libyuv.h"
1.20 +#include "./psnr.h"
1.21 +#include "./ssim.h"
1.22 +
1.23 +int main(int argc, const char* argv[]) {
1.24 + int cpu_flags = TestCpuFlag(-1);
1.25 + int has_arm = TestCpuFlag(kCpuHasARM);
1.26 + int has_mips = TestCpuFlag(kCpuHasMIPS);
1.27 + int has_x86 = TestCpuFlag(kCpuHasX86);
1.28 +#if defined(__i386__) || defined(__x86_64__) || \
1.29 + defined(_M_IX86) || defined(_M_X64)
1.30 + if (has_x86) {
1.31 + uint32 family, model, cpu_info[4];
1.32 + // Vendor ID:
1.33 + // AuthenticAMD AMD processor
1.34 + // CentaurHauls Centaur processor
1.35 + // CyrixInstead Cyrix processor
1.36 + // GenuineIntel Intel processor
1.37 + // GenuineTMx86 Transmeta processor
1.38 + // Geode by NSC National Semiconductor processor
1.39 + // NexGenDriven NexGen processor
1.40 + // RiseRiseRise Rise Technology processor
1.41 + // SiS SiS SiS SiS processor
1.42 + // UMC UMC UMC UMC processor
1.43 + CpuId(0, 0, &cpu_info[0]);
1.44 + cpu_info[0] = cpu_info[1]; // Reorder output
1.45 + cpu_info[1] = cpu_info[3];
1.46 + cpu_info[3] = 0;
1.47 + printf("Cpu Vendor: %s\n", (char*)(&cpu_info[0]));
1.48 +
1.49 + // CPU Family and Model
1.50 + // 3:0 - Stepping
1.51 + // 7:4 - Model
1.52 + // 11:8 - Family
1.53 + // 13:12 - Processor Type
1.54 + // 19:16 - Extended Model
1.55 + // 27:20 - Extended Family
1.56 + CpuId(1, 0, &cpu_info[0]);
1.57 + family = ((cpu_info[0] >> 8) & 0x0f) | ((cpu_info[0] >> 16) & 0xff0);
1.58 + model = ((cpu_info[0] >> 4) & 0x0f) | ((cpu_info[0] >> 12) & 0xf0);
1.59 + printf("Cpu Family %d (0x%x), Model %d (0x%x)\n", family, family,
1.60 + model, model);
1.61 + }
1.62 +#endif
1.63 + printf("Cpu Flags %x\n", cpu_flags);
1.64 + printf("Has ARM %x\n", has_arm);
1.65 + printf("Has MIPS %x\n", has_mips);
1.66 + printf("Has X86 %x\n", has_x86);
1.67 + if (has_arm) {
1.68 + int has_neon = TestCpuFlag(kCpuHasNEON);
1.69 + printf("Has NEON %x\n", has_neon);
1.70 + }
1.71 + if (has_mips) {
1.72 + int has_mips_dsp = TestCpuFlag(kCpuHasMIPS_DSP);
1.73 + int has_mips_dspr2 = TestCpuFlag(kCpuHasMIPS_DSPR2);
1.74 + printf("Has MIPS DSP %x\n", has_mips_dsp);
1.75 + printf("Has MIPS DSPR2 %x\n", has_mips_dspr2);
1.76 + }
1.77 + if (has_x86) {
1.78 + int has_sse2 = TestCpuFlag(kCpuHasSSE2);
1.79 + int has_ssse3 = TestCpuFlag(kCpuHasSSSE3);
1.80 + int has_sse41 = TestCpuFlag(kCpuHasSSE41);
1.81 + int has_sse42 = TestCpuFlag(kCpuHasSSE42);
1.82 + int has_avx = TestCpuFlag(kCpuHasAVX);
1.83 + int has_avx2 = TestCpuFlag(kCpuHasAVX2);
1.84 + int has_erms = TestCpuFlag(kCpuHasERMS);
1.85 + int has_fma3 = TestCpuFlag(kCpuHasFMA3);
1.86 + printf("Has SSE2 %x\n", has_sse2);
1.87 + printf("Has SSSE3 %x\n", has_ssse3);
1.88 + printf("Has SSE4.1 %x\n", has_sse41);
1.89 + printf("Has SSE4.2 %x\n", has_sse42);
1.90 + printf("Has AVX %x\n", has_avx);
1.91 + printf("Has AVX2 %x\n", has_avx2);
1.92 + printf("Has ERMS %x\n", has_erms);
1.93 + printf("Has FMA3 %x\n", has_fma3);
1.94 + }
1.95 + return 0;
1.96 +}
1.97 +
