1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/security/sandbox/chromium/base/atomicops.h Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,164 @@
1.4 +// Copyright (c) 2012 The Chromium Authors. All rights reserved.
1.5 +// Use of this source code is governed by a BSD-style license that can be
1.6 +// found in the LICENSE file.
1.7 +
1.8 +// For atomic operations on reference counts, see atomic_refcount.h.
1.9 +// For atomic operations on sequence numbers, see atomic_sequence_num.h.
1.10 +
1.11 +// The routines exported by this module are subtle. If you use them, even if
1.12 +// you get the code right, it will depend on careful reasoning about atomicity
1.13 +// and memory ordering; it will be less readable, and harder to maintain. If
1.14 +// you plan to use these routines, you should have a good reason, such as solid
1.15 +// evidence that performance would otherwise suffer, or there being no
1.16 +// alternative. You should assume only properties explicitly guaranteed by the
1.17 +// specifications in this file. You are almost certainly _not_ writing code
1.18 +// just for the x86; if you assume x86 semantics, x86 hardware bugs and
1.19 +// implementations on other archtectures will cause your code to break. If you
1.20 +// do not know what you are doing, avoid these routines, and use a Mutex.
1.21 +//
1.22 +// It is incorrect to make direct assignments to/from an atomic variable.
1.23 +// You should use one of the Load or Store routines. The NoBarrier
1.24 +// versions are provided when no barriers are needed:
1.25 +// NoBarrier_Store()
1.26 +// NoBarrier_Load()
1.27 +// Although there are currently no compiler enforcement, you are encouraged
1.28 +// to use these.
1.29 +//
1.30 +
1.31 +#ifndef BASE_ATOMICOPS_H_
1.32 +#define BASE_ATOMICOPS_H_
1.33 +
1.34 +#include "base/basictypes.h"
1.35 +#include "build/build_config.h"
1.36 +
1.37 +#if defined(OS_WIN) && defined(ARCH_CPU_64_BITS)
1.38 +// windows.h #defines this (only on x64). This causes problems because the
1.39 +// public API also uses MemoryBarrier at the public name for this fence. So, on
1.40 +// X64, undef it, and call its documented
1.41 +// (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx)
1.42 +// implementation directly.
1.43 +#undef MemoryBarrier
1.44 +#endif
1.45 +
1.46 +namespace base {
1.47 +namespace subtle {
1.48 +
1.49 +typedef int32 Atomic32;
1.50 +#ifdef ARCH_CPU_64_BITS
1.51 +// We need to be able to go between Atomic64 and AtomicWord implicitly. This
1.52 +// means Atomic64 and AtomicWord should be the same type on 64-bit.
1.53 +#if defined(__ILP32__) || defined(OS_NACL)
1.54 +// NaCl's intptr_t is not actually 64-bits on 64-bit!
1.55 +// http://code.google.com/p/nativeclient/issues/detail?id=1162
1.56 +typedef int64_t Atomic64;
1.57 +#else
1.58 +typedef intptr_t Atomic64;
1.59 +#endif
1.60 +#endif
1.61 +
1.62 +// Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or
1.63 +// Atomic64 routines below, depending on your architecture.
1.64 +typedef intptr_t AtomicWord;
1.65 +
1.66 +// Atomically execute:
1.67 +// result = *ptr;
1.68 +// if (*ptr == old_value)
1.69 +// *ptr = new_value;
1.70 +// return result;
1.71 +//
1.72 +// I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
1.73 +// Always return the old value of "*ptr"
1.74 +//
1.75 +// This routine implies no memory barriers.
1.76 +Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
1.77 + Atomic32 old_value,
1.78 + Atomic32 new_value);
1.79 +
1.80 +// Atomically store new_value into *ptr, returning the previous value held in
1.81 +// *ptr. This routine implies no memory barriers.
1.82 +Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value);
1.83 +
1.84 +// Atomically increment *ptr by "increment". Returns the new value of
1.85 +// *ptr with the increment applied. This routine implies no memory barriers.
1.86 +Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment);
1.87 +
1.88 +Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
1.89 + Atomic32 increment);
1.90 +
1.91 +// These following lower-level operations are typically useful only to people
1.92 +// implementing higher-level synchronization operations like spinlocks,
1.93 +// mutexes, and condition-variables. They combine CompareAndSwap(), a load, or
1.94 +// a store with appropriate memory-ordering instructions. "Acquire" operations
1.95 +// ensure that no later memory access can be reordered ahead of the operation.
1.96 +// "Release" operations ensure that no previous memory access can be reordered
1.97 +// after the operation. "Barrier" operations have both "Acquire" and "Release"
1.98 +// semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
1.99 +// access.
1.100 +Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
1.101 + Atomic32 old_value,
1.102 + Atomic32 new_value);
1.103 +Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
1.104 + Atomic32 old_value,
1.105 + Atomic32 new_value);
1.106 +
1.107 +void MemoryBarrier();
1.108 +void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value);
1.109 +void Acquire_Store(volatile Atomic32* ptr, Atomic32 value);
1.110 +void Release_Store(volatile Atomic32* ptr, Atomic32 value);
1.111 +
1.112 +Atomic32 NoBarrier_Load(volatile const Atomic32* ptr);
1.113 +Atomic32 Acquire_Load(volatile const Atomic32* ptr);
1.114 +Atomic32 Release_Load(volatile const Atomic32* ptr);
1.115 +
1.116 +// 64-bit atomic operations (only available on 64-bit processors).
1.117 +#ifdef ARCH_CPU_64_BITS
1.118 +Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
1.119 + Atomic64 old_value,
1.120 + Atomic64 new_value);
1.121 +Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value);
1.122 +Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
1.123 +Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
1.124 +
1.125 +Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
1.126 + Atomic64 old_value,
1.127 + Atomic64 new_value);
1.128 +Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
1.129 + Atomic64 old_value,
1.130 + Atomic64 new_value);
1.131 +void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value);
1.132 +void Acquire_Store(volatile Atomic64* ptr, Atomic64 value);
1.133 +void Release_Store(volatile Atomic64* ptr, Atomic64 value);
1.134 +Atomic64 NoBarrier_Load(volatile const Atomic64* ptr);
1.135 +Atomic64 Acquire_Load(volatile const Atomic64* ptr);
1.136 +Atomic64 Release_Load(volatile const Atomic64* ptr);
1.137 +#endif // ARCH_CPU_64_BITS
1.138 +
1.139 +} // namespace base::subtle
1.140 +} // namespace base
1.141 +
1.142 +// Include our platform specific implementation.
1.143 +#if defined(THREAD_SANITIZER)
1.144 +#include "base/atomicops_internals_tsan.h"
1.145 +#elif defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)
1.146 +#include "base/atomicops_internals_x86_msvc.h"
1.147 +#elif defined(OS_MACOSX)
1.148 +#include "base/atomicops_internals_mac.h"
1.149 +#elif defined(OS_NACL)
1.150 +#include "base/atomicops_internals_gcc.h"
1.151 +#elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)
1.152 +#include "base/atomicops_internals_arm_gcc.h"
1.153 +#elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY)
1.154 +#include "base/atomicops_internals_x86_gcc.h"
1.155 +#elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS_FAMILY)
1.156 +#include "base/atomicops_internals_mips_gcc.h"
1.157 +#else
1.158 +#error "Atomic operations are not supported on your platform"
1.159 +#endif
1.160 +
1.161 +// On some platforms we need additional declarations to make
1.162 +// AtomicWord compatible with our other Atomic* types.
1.163 +#if defined(OS_MACOSX) || defined(OS_OPENBSD)
1.164 +#include "base/atomicops_internals_atomicword_compat.h"
1.165 +#endif
1.166 +
1.167 +#endif // BASE_ATOMICOPS_H_
