1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/toolkit/crashreporter/google-breakpad/src/third_party/libdisasm/ia32_insn.h Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,506 @@
1.4 +#ifndef IA32_INSN_H
1.5 +#define IA32_INSN_H
1.6 +/* this file contains the structure of opcode definitions and the
1.7 + * constants they use */
1.8 +
1.9 +#include <sys/types.h>
1.10 +#include "libdis.h"
1.11 +
1.12 +
1.13 +#define GET_BYTE( buf, buf_len ) buf_len ? *buf : 0
1.14 +
1.15 +#define OP_SIZE_16 1
1.16 +#define OP_SIZE_32 2
1.17 +#define ADDR_SIZE_16 4
1.18 +#define ADDR_SIZE_32 8
1.19 +
1.20 +#define MAX_INSTRUCTION_SIZE 20
1.21 +
1.22 +/* invalid instructions are handled by returning 0 [error] from the
1.23 + * function, setting the size of the insn to 1 byte, and copying
1.24 + * the byte at the start of the invalid insn into the x86_insn_t.
1.25 + * if the caller is saving the x86_insn_t for invalid instructions,
1.26 + * instead of discarding them, this will maintain a consistent
1.27 + * address space in the x86_insn_ts */
1.28 +
1.29 +#define INVALID_INSN ((size_t) -1) /* return value for invalid insn */
1.30 +#define MAKE_INVALID( i, buf ) \
1.31 + strcpy( i->mnemonic, "invalid" ); \
1.32 + x86_oplist_free( i ); \
1.33 + i->size = 1; \
1.34 + i->group = insn_none; \
1.35 + i->type = insn_invalid; \
1.36 + memcpy( i->bytes, buf, 1 );
1.37 +
1.38 +
1.39 +size_t ia32_disasm_addr( unsigned char * buf, size_t buf_len,
1.40 + x86_insn_t *insn);
1.41 +
1.42 +
1.43 +/* --------------------------------------------------------- Table Lookup */
1.44 +/* IA32 Instruction defintion for ia32_opcodes.c */
1.45 +typedef struct {
1.46 + unsigned int table; /* escape to this sub-table */
1.47 + unsigned int mnem_flag; /* Flags referring to mnemonic */
1.48 + unsigned int notes; /* Notes for this instruction */
1.49 + unsigned int dest_flag, src_flag, aux_flag; /* and for specific operands */
1.50 + unsigned int cpu; /* minimumCPU [AND with clocks?? */
1.51 + char mnemonic[16]; /* buffers for building instruction */
1.52 + char mnemonic_att[16]; /* at&t style mnemonic name */
1.53 + int32_t dest;
1.54 + int32_t src;
1.55 + int32_t aux;
1.56 + unsigned int flags_effected;
1.57 + unsigned int implicit_ops; /* implicit operands */
1.58 +} ia32_insn_t;
1.59 +
1.60 +
1.61 +
1.62 +/* --------------------------------------------------------- Prefixes */
1.63 +/* Prefix Flags */
1.64 +/* Prefixes, same order as in the manual */
1.65 +/* had to reverse the values of the first three as they were entered into
1.66 + * libdis.h incorrectly. */
1.67 +#define PREFIX_LOCK 0x0004
1.68 +#define PREFIX_REPNZ 0x0002
1.69 +#define PREFIX_REPZ 0x0001
1.70 +#define PREFIX_OP_SIZE 0x0010
1.71 +#define PREFIX_ADDR_SIZE 0x0020
1.72 +#define PREFIX_CS 0x0100
1.73 +#define PREFIX_SS 0x0200
1.74 +#define PREFIX_DS 0x0300
1.75 +#define PREFIX_ES 0x0400
1.76 +#define PREFIX_FS 0x0500
1.77 +#define PREFIX_GS 0x0600
1.78 +#define PREFIX_TAKEN 0x1000 /* branch taken */
1.79 +#define PREFIX_NOTTAKEN 0x2000 /* branch not taken */
1.80 +#define PREFIX_REG_MASK 0x0F00
1.81 +#define BRANCH_HINT_MASK 0x3000
1.82 +#define PREFIX_PRINT_MASK 0x000F /* printable prefixes */
1.83 +#define PREFIX_MASK 0xFFFF
1.84 +
1.85 +/* ---------------------------------------------------------- CPU Type */
1.86 +
1.87 +#define cpu_8086 0x0001
1.88 +#define cpu_80286 0x0002
1.89 +#define cpu_80386 0x0003
1.90 +#define cpu_80387 0x0004 /* originally these were a co-proc */
1.91 +#define cpu_80486 0x0005
1.92 +#define cpu_PENTIUM 0x0006
1.93 +#define cpu_PENTPRO 0x0007
1.94 +#define cpu_PENTIUM2 0x0008
1.95 +#define cpu_PENTIUM3 0x0009
1.96 +#define cpu_PENTIUM4 0x000A
1.97 +#define cpu_K6 0x0010
1.98 +#define cpu_K7 0x0020
1.99 +#define cpu_ATHLON 0x0030
1.100 +#define CPU_MODEL_MASK 0xFFFF
1.101 +#define CPU_MODEL(cpu) (cpu & CPU_MODEL_MASK)
1.102 +/* intel instruction subsets */
1.103 +#define isa_GP 0x10000 /* General Purpose Instructions */
1.104 +#define isa_FPU 0x20000 /* FPU instructions */
1.105 +#define isa_FPUMGT 0x30000 /* FPU/SIMD Management */
1.106 +#define isa_MMX 0x40000 /* MMX */
1.107 +#define isa_SSE1 0x50000 /* SSE */
1.108 +#define isa_SSE2 0x60000 /* SSE 2 */
1.109 +#define isa_SSE3 0x70000 /* SSE 3 */
1.110 +#define isa_3DNOW 0x80000 /* AMD 3d Now */
1.111 +#define isa_SYS 0x90000 /* System Instructions */
1.112 +#define ISA_SUBSET_MASK 0xFFFF0000
1.113 +#define ISA_SUBSET(isa) (isa & ISA_SUBSET_MASK)
1.114 +
1.115 +
1.116 +/* ------------------------------------------------------ Operand Decoding */
1.117 +#define ARG_NONE 0
1.118 +
1.119 +/* Using a mask allows us to store info such as OP_SIGNED in the
1.120 + * operand flags field */
1.121 +#define OPFLAGS_MASK 0x0000FFFF
1.122 +
1.123 +/* Operand Addressing Methods, per intel manual */
1.124 +#define ADDRMETH_MASK 0x00FF0000
1.125 +
1.126 +/* note: for instructions with implied operands, use no ADDRMETH */
1.127 +#define ADDRMETH_A 0x00010000
1.128 +#define ADDRMETH_C 0x00020000
1.129 +#define ADDRMETH_D 0x00030000
1.130 +#define ADDRMETH_E 0x00040000
1.131 +#define ADDRMETH_F 0x00050000
1.132 +#define ADDRMETH_G 0x00060000
1.133 +#define ADDRMETH_I 0x00070000
1.134 +#define ADDRMETH_J 0x00080000
1.135 +#define ADDRMETH_M 0x00090000
1.136 +#define ADDRMETH_O 0x000A0000
1.137 +#define ADDRMETH_P 0x000B0000
1.138 +#define ADDRMETH_Q 0x000C0000
1.139 +#define ADDRMETH_R 0x000D0000
1.140 +#define ADDRMETH_S 0x000E0000
1.141 +#define ADDRMETH_T 0x000F0000
1.142 +#define ADDRMETH_V 0x00100000
1.143 +#define ADDRMETH_W 0x00110000
1.144 +#define ADDRMETH_X 0x00120000
1.145 +#define ADDRMETH_Y 0x00130000
1.146 +#define ADDRMETH_RR 0x00140000 /* gen reg hard-coded in opcode */
1.147 +#define ADDRMETH_RS 0x00150000 /* seg reg hard-coded in opcode */
1.148 +#define ADDRMETH_RT 0x00160000 /* test reg hard-coded in opcode */
1.149 +#define ADDRMETH_RF 0x00170000 /* fpu reg hard-coded in opcode */
1.150 +#define ADDRMETH_II 0x00180000 /* immediate hard-coded in opcode */
1.151 +#define ADDRMETH_PP 0x00190000 /* mm reg ONLY in modr/m field */
1.152 +#define ADDRMETH_VV 0x001A0000 /* xmm reg ONLY in mod/rm field */
1.153 +
1.154 +/* Operand Types, per intel manual */
1.155 +#define OPTYPE_MASK 0xFF000000
1.156 +
1.157 +#define OPTYPE_a 0x01000000 /* BOUND: h:h or w:w */
1.158 +#define OPTYPE_b 0x02000000 /* byte */
1.159 +#define OPTYPE_c 0x03000000 /* byte or word */
1.160 +#define OPTYPE_d 0x04000000 /* word */
1.161 +#define OPTYPE_dq 0x05000000 /* qword */
1.162 +#define OPTYPE_p 0x06000000 /* 16:16 or 16:32 pointer */
1.163 +#define OPTYPE_pi 0x07000000 /* dword MMX reg */
1.164 +#define OPTYPE_ps 0x08000000 /* 128-bit single fp */
1.165 +#define OPTYPE_q 0x09000000 /* dword */
1.166 +#define OPTYPE_s 0x0A000000 /* 6-byte descriptor */
1.167 +#define OPTYPE_ss 0x0B000000 /* scalar of 128-bit single fp */
1.168 +#define OPTYPE_si 0x0C000000 /* word general register */
1.169 +#define OPTYPE_v 0x0D000000 /* hword or word */
1.170 +#define OPTYPE_w 0x0E000000 /* hword */
1.171 +#define OPTYPE_m 0x0F000000 /* to handle LEA */
1.172 +#define OPTYPE_none 0xFF000000 /* no valid operand size, INVLPG */
1.173 +
1.174 +/* custom ones for FPU instructions */
1.175 +#define OPTYPE_fs 0x10000000 /* pointer to single-real*/
1.176 +#define OPTYPE_fd 0x20000000 /* pointer to double real */
1.177 +#define OPTYPE_fe 0x30000000 /* pointer to extended real */
1.178 +#define OPTYPE_fb 0x40000000 /* pointer to packed BCD */
1.179 +#define OPTYPE_fv 0x50000000 /* pointer to FPU env: 14|28-bytes */
1.180 +#define OPTYPE_ft 0x60000000 /* pointer to FPU state: 94|108-bytes */
1.181 +#define OPTYPE_fx 0x70000000 /* pointer to FPU regs: 512 bites */
1.182 +#define OPTYPE_fp 0x80000000 /* general fpu register: dbl ext */
1.183 +
1.184 +/* SSE2 operand types */
1.185 +#define OPTYPE_sd 0x90000000 /* scalar of 128-bit double fp */
1.186 +#define OPTYPE_pd 0xA0000000 /* 128-bit double fp */
1.187 +
1.188 +
1.189 +
1.190 +/* ---------------------------------------------- Opcode Table Descriptions */
1.191 +/* the table type describes how to handle byte/size increments before
1.192 + * and after lookup. Some tables re-use the current byte, others
1.193 + * consume a byte only if the ModR/M encodes no operands, etc */
1.194 +enum ia32_tbl_type_id {
1.195 + tbl_opcode = 0, /* standard opcode table: no surprises */
1.196 + tbl_prefix, /* Prefix Override, e.g. 66/F2/F3 */
1.197 + tbl_suffix, /* 3D Now style */
1.198 + tbl_extension, /* ModR/M extension: 00-FF -> 00-07 */
1.199 + tbl_ext_ext, /* extension of modr/m using R/M field */
1.200 + tbl_fpu, /* fpu table: 00-BF -> 00-0F */
1.201 + tbl_fpu_ext /* fpu extension : C0-FF -> 00-1F */
1.202 + };
1.203 +
1.204 +/* How it works:
1.205 + * Bytes are 'consumed' if the next table lookup requires that the byte
1.206 + * pointer be advanced in the instruction stream. 'Does not consume' means
1.207 + * that, when the lookup function recurses, the same byte it re-used in the
1.208 + * new table. It also means that size is not decremented, for example when
1.209 + * a ModR/M byte is used. Note that tbl_extension (ModR/M) instructions that
1.210 + * do not increase the size of an insn with their operands have a forced
1.211 + 3 size increase in the lookup algo. Weird, yes, confusing, yes, welcome
1.212 + * to the Intel ISA. Another note: tbl_prefix is used as an override, so an
1.213 + * empty insn in a prefix table causes the instruction in the original table
1.214 + * to be used, rather than an invalid insn being generated.
1.215 + * tbl_opcode uses current byte and consumes it
1.216 + * tbl_prefix uses current byte but does not consume it
1.217 + * tbl_suffix uses and consumes last byte in insn
1.218 + * tbl_extension uses current byte but does not consume it
1.219 + * tbl_ext_ext uses current byte but does not consume it
1.220 + * tbl_fpu uses current byte and consumes it
1.221 + * tbl_fpu_ext uses current byte but does not consume it
1.222 + */
1.223 +
1.224 +/* Convenience struct for opcode tables : these will be stored in a
1.225 + * 'table of tables' so we can use a table index instead of a pointer */
1.226 +typedef struct { /* Assembly instruction tables */
1.227 + ia32_insn_t *table; /* Pointer to table of instruction encodings */
1.228 + enum ia32_tbl_type_id type;
1.229 + unsigned char shift; /* amount to shift modrm byte */
1.230 + unsigned char mask; /* bit mask for look up */
1.231 + unsigned char minlim,maxlim; /* limits on min/max entries. */
1.232 +} ia32_table_desc_t;
1.233 +
1.234 +
1.235 +/* ---------------------------------------------- 'Cooked' Operand Type Info */
1.236 +/* Permissions: */
1.237 +#define OP_R 0x001 /* operand is READ */
1.238 +#define OP_W 0x002 /* operand is WRITTEN */
1.239 +#define OP_RW 0x003 /* (OP_R|OP_W): convenience macro */
1.240 +#define OP_X 0x004 /* operand is EXECUTED */
1.241 +
1.242 +#define OP_PERM_MASK 0x0000007 /* perms are NOT mutually exclusive */
1.243 +#define OP_PERM( type ) (type & OP_PERM_MASK)
1.244 +
1.245 +/* Flags */
1.246 +#define OP_SIGNED 0x010 /* operand is signed */
1.247 +
1.248 +#define OP_FLAG_MASK 0x0F0 /* mods are NOT mutually exclusive */
1.249 +#define OP_FLAGS( type ) (type & OP_FLAG_MASK)
1.250 +
1.251 +#define OP_REG_MASK 0x0000FFFF /* lower WORD is register ID */
1.252 +#define OP_REGTBL_MASK 0xFFFF0000 /* higher word is register type [gen/dbg] */
1.253 +#define OP_REGID( type ) (type & OP_REG_MASK)
1.254 +#define OP_REGTYPE( type ) (type & OP_REGTBL_MASK)
1.255 +
1.256 +/* ------------------------------------------'Cooked' Instruction Type Info */
1.257 +/* high-bit opcode types/insn meta-types */
1.258 +#define INS_FLAG_PREFIX 0x10000000 /* insn is a prefix */
1.259 +#define INS_FLAG_SUFFIX 0x20000000 /* followed by a suffix byte */
1.260 +#define INS_FLAG_MASK 0xFF000000
1.261 +
1.262 +/* insn notes */
1.263 +#define INS_NOTE_RING0 0x00000001 /* insn is privileged */
1.264 +#define INS_NOTE_SMM 0x00000002 /* Sys Mgt Mode only */
1.265 +#define INS_NOTE_SERIAL 0x00000004 /* serializes */
1.266 +#define INS_NOTE_NONSWAP 0x00000008 /* insn is not swapped in att format */ // could be separate field?
1.267 +#define INS_NOTE_NOSUFFIX 0x00000010 /* insn has no size suffix in att format */ // could be separate field?
1.268 +//#define INS_NOTE_NMI
1.269 +
1.270 +#define INS_INVALID 0
1.271 +
1.272 +/* instruction groups */
1.273 +#define INS_EXEC 0x1000
1.274 +#define INS_ARITH 0x2000
1.275 +#define INS_LOGIC 0x3000
1.276 +#define INS_STACK 0x4000
1.277 +#define INS_COND 0x5000
1.278 +#define INS_LOAD 0x6000
1.279 +#define INS_ARRAY 0x7000
1.280 +#define INS_BIT 0x8000
1.281 +#define INS_FLAG 0x9000
1.282 +#define INS_FPU 0xA000
1.283 +#define INS_TRAPS 0xD000
1.284 +#define INS_SYSTEM 0xE000
1.285 +#define INS_OTHER 0xF000
1.286 +
1.287 +#define INS_GROUP_MASK 0xF000
1.288 +#define INS_GROUP( type ) ( type & INS_GROUP_MASK )
1.289 +
1.290 +/* INS_EXEC group */
1.291 +#define INS_BRANCH (INS_EXEC | 0x01) /* Unconditional branch */
1.292 +#define INS_BRANCHCC (INS_EXEC | 0x02) /* Conditional branch */
1.293 +#define INS_CALL (INS_EXEC | 0x03) /* Jump to subroutine */
1.294 +#define INS_CALLCC (INS_EXEC | 0x04) /* Jump to subroutine */
1.295 +#define INS_RET (INS_EXEC | 0x05) /* Return from subroutine */
1.296 +
1.297 +/* INS_ARITH group */
1.298 +#define INS_ADD (INS_ARITH | 0x01)
1.299 +#define INS_SUB (INS_ARITH | 0x02)
1.300 +#define INS_MUL (INS_ARITH | 0x03)
1.301 +#define INS_DIV (INS_ARITH | 0x04)
1.302 +#define INS_INC (INS_ARITH | 0x05) /* increment */
1.303 +#define INS_DEC (INS_ARITH | 0x06) /* decrement */
1.304 +#define INS_SHL (INS_ARITH | 0x07) /* shift right */
1.305 +#define INS_SHR (INS_ARITH | 0x08) /* shift left */
1.306 +#define INS_ROL (INS_ARITH | 0x09) /* rotate left */
1.307 +#define INS_ROR (INS_ARITH | 0x0A) /* rotate right */
1.308 +#define INS_MIN (INS_ARITH | 0x0B) /* min func */
1.309 +#define INS_MAX (INS_ARITH | 0x0C) /* max func */
1.310 +#define INS_AVG (INS_ARITH | 0x0D) /* avg func */
1.311 +#define INS_FLR (INS_ARITH | 0x0E) /* floor func */
1.312 +#define INS_CEIL (INS_ARITH | 0x0F) /* ceiling func */
1.313 +
1.314 +/* INS_LOGIC group */
1.315 +#define INS_AND (INS_LOGIC | 0x01)
1.316 +#define INS_OR (INS_LOGIC | 0x02)
1.317 +#define INS_XOR (INS_LOGIC | 0x03)
1.318 +#define INS_NOT (INS_LOGIC | 0x04)
1.319 +#define INS_NEG (INS_LOGIC | 0x05)
1.320 +#define INS_NAND (INS_LOGIC | 0x06)
1.321 +
1.322 +/* INS_STACK group */
1.323 +#define INS_PUSH (INS_STACK | 0x01)
1.324 +#define INS_POP (INS_STACK | 0x02)
1.325 +#define INS_PUSHREGS (INS_STACK | 0x03) /* push register context */
1.326 +#define INS_POPREGS (INS_STACK | 0x04) /* pop register context */
1.327 +#define INS_PUSHFLAGS (INS_STACK | 0x05) /* push all flags */
1.328 +#define INS_POPFLAGS (INS_STACK | 0x06) /* pop all flags */
1.329 +#define INS_ENTER (INS_STACK | 0x07) /* enter stack frame */
1.330 +#define INS_LEAVE (INS_STACK | 0x08) /* leave stack frame */
1.331 +
1.332 +/* INS_COND group */
1.333 +#define INS_TEST (INS_COND | 0x01)
1.334 +#define INS_CMP (INS_COND | 0x02)
1.335 +
1.336 +/* INS_LOAD group */
1.337 +#define INS_MOV (INS_LOAD | 0x01)
1.338 +#define INS_MOVCC (INS_LOAD | 0x02)
1.339 +#define INS_XCHG (INS_LOAD | 0x03)
1.340 +#define INS_XCHGCC (INS_LOAD | 0x04)
1.341 +#define INS_CONV (INS_LOAD | 0x05) /* move and convert type */
1.342 +
1.343 +/* INS_ARRAY group */
1.344 +#define INS_STRCMP (INS_ARRAY | 0x01)
1.345 +#define INS_STRLOAD (INS_ARRAY | 0x02)
1.346 +#define INS_STRMOV (INS_ARRAY | 0x03)
1.347 +#define INS_STRSTOR (INS_ARRAY | 0x04)
1.348 +#define INS_XLAT (INS_ARRAY | 0x05)
1.349 +
1.350 +/* INS_BIT group */
1.351 +#define INS_BITTEST (INS_BIT | 0x01)
1.352 +#define INS_BITSET (INS_BIT | 0x02)
1.353 +#define INS_BITCLR (INS_BIT | 0x03)
1.354 +
1.355 +/* INS_FLAG group */
1.356 +#define INS_CLEARCF (INS_FLAG | 0x01) /* clear Carry flag */
1.357 +#define INS_CLEARZF (INS_FLAG | 0x02) /* clear Zero flag */
1.358 +#define INS_CLEAROF (INS_FLAG | 0x03) /* clear Overflow flag */
1.359 +#define INS_CLEARDF (INS_FLAG | 0x04) /* clear Direction flag */
1.360 +#define INS_CLEARSF (INS_FLAG | 0x05) /* clear Sign flag */
1.361 +#define INS_CLEARPF (INS_FLAG | 0x06) /* clear Parity flag */
1.362 +#define INS_SETCF (INS_FLAG | 0x07)
1.363 +#define INS_SETZF (INS_FLAG | 0x08)
1.364 +#define INS_SETOF (INS_FLAG | 0x09)
1.365 +#define INS_SETDF (INS_FLAG | 0x0A)
1.366 +#define INS_SETSF (INS_FLAG | 0x0B)
1.367 +#define INS_SETPF (INS_FLAG | 0x0C)
1.368 +#define INS_TOGCF (INS_FLAG | 0x10) /* toggle */
1.369 +#define INS_TOGZF (INS_FLAG | 0x20)
1.370 +#define INS_TOGOF (INS_FLAG | 0x30)
1.371 +#define INS_TOGDF (INS_FLAG | 0x40)
1.372 +#define INS_TOGSF (INS_FLAG | 0x50)
1.373 +#define INS_TOGPF (INS_FLAG | 0x60)
1.374 +
1.375 +/* INS_FPU */
1.376 +#define INS_FMOV (INS_FPU | 0x1)
1.377 +#define INS_FMOVCC (INS_FPU | 0x2)
1.378 +#define INS_FNEG (INS_FPU | 0x3)
1.379 +#define INS_FABS (INS_FPU | 0x4)
1.380 +#define INS_FADD (INS_FPU | 0x5)
1.381 +#define INS_FSUB (INS_FPU | 0x6)
1.382 +#define INS_FMUL (INS_FPU | 0x7)
1.383 +#define INS_FDIV (INS_FPU | 0x8)
1.384 +#define INS_FSQRT (INS_FPU | 0x9)
1.385 +#define INS_FCMP (INS_FPU | 0xA)
1.386 +#define INS_FCOS (INS_FPU | 0xC) /* cosine */
1.387 +#define INS_FLDPI (INS_FPU | 0xD) /* load pi */
1.388 +#define INS_FLDZ (INS_FPU | 0xE) /* load 0 */
1.389 +#define INS_FTAN (INS_FPU | 0xF) /* tanget */
1.390 +#define INS_FSINE (INS_FPU | 0x10) /* sine */
1.391 +#define INS_FSYS (INS_FPU | 0x20) /* misc */
1.392 +
1.393 +/* INS_TRAP */
1.394 +#define INS_TRAP (INS_TRAPS | 0x01) /* generate trap */
1.395 +#define INS_TRAPCC (INS_TRAPS | 0x02) /* conditional trap gen */
1.396 +#define INS_TRET (INS_TRAPS | 0x03) /* return from trap */
1.397 +#define INS_BOUNDS (INS_TRAPS | 0x04) /* gen bounds trap */
1.398 +#define INS_DEBUG (INS_TRAPS | 0x05) /* gen breakpoint trap */
1.399 +#define INS_TRACE (INS_TRAPS | 0x06) /* gen single step trap */
1.400 +#define INS_INVALIDOP (INS_TRAPS | 0x07) /* gen invalid insn */
1.401 +#define INS_OFLOW (INS_TRAPS | 0x08) /* gen overflow trap */
1.402 +#define INS_ICEBP (INS_TRAPS | 0x09) /* ICE breakpoint */
1.403 +
1.404 +/* INS_SYSTEM */
1.405 +#define INS_HALT (INS_SYSTEM | 0x01) /* halt machine */
1.406 +#define INS_IN (INS_SYSTEM | 0x02) /* input form port */
1.407 +#define INS_OUT (INS_SYSTEM | 0x03) /* output to port */
1.408 +#define INS_CPUID (INS_SYSTEM | 0x04) /* identify cpu */
1.409 +
1.410 +/* INS_OTHER */
1.411 +#define INS_NOP (INS_OTHER | 0x01)
1.412 +#define INS_BCDCONV (INS_OTHER | 0x02) /* convert to/from BCD */
1.413 +#define INS_SZCONV (INS_OTHER | 0x03) /* convert size of operand */
1.414 +#define INS_SALC (INS_OTHER | 0x04) /* set %al on carry */
1.415 +#define INS_UNKNOWN (INS_OTHER | 0x05)
1.416 +
1.417 +
1.418 +#define INS_TYPE_MASK 0xFFFF
1.419 +#define INS_TYPE( type ) ( type & INS_TYPE_MASK )
1.420 +
1.421 + /* flags effected by instruction */
1.422 +#define INS_TEST_CARRY 0x01 /* carry */
1.423 +#define INS_TEST_ZERO 0x02 /* zero/equal */
1.424 +#define INS_TEST_OFLOW 0x04 /* overflow */
1.425 +#define INS_TEST_DIR 0x08 /* direction */
1.426 +#define INS_TEST_SIGN 0x10 /* negative */
1.427 +#define INS_TEST_PARITY 0x20 /* parity */
1.428 +#define INS_TEST_OR 0x40 /* used in jle */
1.429 +#define INS_TEST_NCARRY 0x100 /* ! carry */
1.430 +#define INS_TEST_NZERO 0x200 /* ! zero */
1.431 +#define INS_TEST_NOFLOW 0x400 /* ! oflow */
1.432 +#define INS_TEST_NDIR 0x800 /* ! dir */
1.433 +#define INS_TEST_NSIGN 0x100 /* ! sign */
1.434 +#define INS_TEST_NPARITY 0x2000 /* ! parity */
1.435 +/* SF == OF */
1.436 +#define INS_TEST_SFEQOF 0x4000
1.437 +/* SF != OF */
1.438 +#define INS_TEST_SFNEOF 0x8000
1.439 +
1.440 +#define INS_TEST_ALL INS_TEST_CARRY | INS_TEST_ZERO | \
1.441 + INS_TEST_OFLOW | INS_TEST_SIGN | \
1.442 + INS_TEST_PARITY
1.443 +
1.444 +#define INS_SET_CARRY 0x010000 /* carry */
1.445 +#define INS_SET_ZERO 0x020000 /* zero/equal */
1.446 +#define INS_SET_OFLOW 0x040000 /* overflow */
1.447 +#define INS_SET_DIR 0x080000 /* direction */
1.448 +#define INS_SET_SIGN 0x100000 /* negative */
1.449 +#define INS_SET_PARITY 0x200000 /* parity */
1.450 +#define INS_SET_NCARRY 0x1000000
1.451 +#define INS_SET_NZERO 0x2000000
1.452 +#define INS_SET_NOFLOW 0x4000000
1.453 +#define INS_SET_NDIR 0x8000000
1.454 +#define INS_SET_NSIGN 0x10000000
1.455 +#define INS_SET_NPARITY 0x20000000
1.456 +#define INS_SET_SFEQOF 0x40000000
1.457 +#define INS_SET_SFNEOF 0x80000000
1.458 +
1.459 +#define INS_SET_ALL INS_SET_CARRY | INS_SET_ZERO | \
1.460 + INS_SET_OFLOW | INS_SET_SIGN | \
1.461 + INS_SET_PARITY
1.462 +
1.463 +#define INS_TEST_MASK 0x0000FFFF
1.464 +#define INS_FLAGS_TEST(x) (x & INS_TEST_MASK)
1.465 +#define INS_SET_MASK 0xFFFF0000
1.466 +#define INS_FLAGS_SET(x) (x & INS_SET_MASK)
1.467 +
1.468 +#if 0
1.469 +/* TODO: actually start using these */
1.470 +#define X86_PAIR_NP 1 /* not pairable; execs in U */
1.471 +#define X86_PAIR_PU 2 /* pairable in U pipe */
1.472 +#define X86_PAIR_PV 3 /* pairable in V pipe */
1.473 +#define X86_PAIR_UV 4 /* pairable in UV pipe */
1.474 +#define X86_PAIR_FX 5 /* pairable with FXCH */
1.475 +
1.476 +#define X86_EXEC_PORT_0 1
1.477 +#define X86_EXEC_PORT_1 2
1.478 +#define X86_EXEC_PORT_2 4
1.479 +#define X86_EXEC_PORT_3 8
1.480 +#define X86_EXEC_PORT_4 16
1.481 +
1.482 +#define X86_EXEC_UNITS
1.483 +
1.484 +typedef struct { /* representation of an insn during decoding */
1.485 + uint32_t flags; /* runtime settings */
1.486 + /* instruction prefixes and other foolishness */
1.487 + uint32_t prefix; /* encoding of prefix */
1.488 + char prefix_str[16]; /* mnemonics for prefix */
1.489 + uint32_t branch_hint; /* gah! */
1.490 + unsigned int cpu_ver; /* TODO: cpu version */
1.491 + unsigned int clocks; /* TODO: clock cycles: min/max */
1.492 + unsigned char last_prefix;
1.493 + /* runtime intruction decoding helpers */
1.494 + unsigned char mode; /* 16, 32, 64 */
1.495 + unsigned char gen_regs; /* offset of default general reg set */
1.496 + unsigned char sz_operand; /* operand size for insn */
1.497 + unsigned char sz_address; /* address size for insn */
1.498 + unsigned char uops; /* uops per insn */
1.499 + unsigned char pairing; /* np,pu,pv.lv */
1.500 + unsigned char exec_unit;
1.501 + unsigned char exec_port;
1.502 + unsigned char latency;
1.503 +} ia32_info_t;
1.504 +#define MODE_32 0 /* default */
1.505 +#define MODE_16 1
1.506 +#define MODE_64 2
1.507 +#endif
1.508 +
1.509 +#endif
