media/libopus/celt/arm/fixed_armv5e.h@ac0c01689b40
media/libopus/celt/arm/fixed_armv5e.h
Thu, 15 Jan 2015 15:59:08 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Thu, 15 Jan 2015 15:59:08 +0100
- branch
- TOR_BUG_9701
- changeset 10
- ac0c01689b40
- permissions
- -rw-r--r--
Implement a real Private Browsing Mode condition by changing the API/ABI;
This solves Tor bug #9701, complying with disk avoidance documented in
https://www.torproject.org/projects/torbrowser/design/#disk-avoidance.
1 /* Copyright (C) 2007-2009 Xiph.Org Foundation
2 Copyright (C) 2003-2008 Jean-Marc Valin
3 Copyright (C) 2007-2008 CSIRO
4 Copyright (C) 2013 Parrot */
5 /*
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
8 are met:
10 - Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
13 - Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
21 OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
30 #ifndef FIXED_ARMv5E_H
31 #define FIXED_ARMv5E_H
33 #include "fixed_armv4.h"
35 /** 16x32 multiplication, followed by a 16-bit shift right. Results fits in 32 bits */
36 #undef MULT16_32_Q16
37 static OPUS_INLINE opus_val32 MULT16_32_Q16_armv5e(opus_val16 a, opus_val32 b)
38 {
39 int res;
40 __asm__(
41 "#MULT16_32_Q16\n\t"
42 "smulwb %0, %1, %2\n\t"
43 : "=r"(res)
44 : "r"(b),"r"(a)
45 );
46 return res;
47 }
48 #define MULT16_32_Q16(a, b) (MULT16_32_Q16_armv5e(a, b))
51 /** 16x32 multiplication, followed by a 15-bit shift right. Results fits in 32 bits */
52 #undef MULT16_32_Q15
53 static OPUS_INLINE opus_val32 MULT16_32_Q15_armv5e(opus_val16 a, opus_val32 b)
54 {
55 int res;
56 __asm__(
57 "#MULT16_32_Q15\n\t"
58 "smulwb %0, %1, %2\n\t"
59 : "=r"(res)
60 : "r"(b), "r"(a)
61 );
62 return res<<1;
63 }
64 #define MULT16_32_Q15(a, b) (MULT16_32_Q15_armv5e(a, b))
67 /** 16x32 multiply, followed by a 15-bit shift right and 32-bit add.
68 b must fit in 31 bits.
69 Result fits in 32 bits. */
70 #undef MAC16_32_Q15
71 static OPUS_INLINE opus_val32 MAC16_32_Q15_armv5e(opus_val32 c, opus_val16 a,
72 opus_val32 b)
73 {
74 int res;
75 __asm__(
76 "#MAC16_32_Q15\n\t"
77 "smlawb %0, %1, %2, %3;\n"
78 : "=r"(res)
79 : "r"(b<<1), "r"(a), "r"(c)
80 );
81 return res;
82 }
83 #define MAC16_32_Q15(c, a, b) (MAC16_32_Q15_armv5e(c, a, b))
85 /** 16x16 multiply-add where the result fits in 32 bits */
86 #undef MAC16_16
87 static OPUS_INLINE opus_val32 MAC16_16_armv5e(opus_val32 c, opus_val16 a,
88 opus_val16 b)
89 {
90 int res;
91 __asm__(
92 "#MAC16_16\n\t"
93 "smlabb %0, %1, %2, %3;\n"
94 : "=r"(res)
95 : "r"(a), "r"(b), "r"(c)
96 );
97 return res;
98 }
99 #define MAC16_16(c, a, b) (MAC16_16_armv5e(c, a, b))
101 /** 16x16 multiplication where the result fits in 32 bits */
102 #undef MULT16_16
103 static OPUS_INLINE opus_val32 MULT16_16_armv5e(opus_val16 a, opus_val16 b)
104 {
105 int res;
106 __asm__(
107 "#MULT16_16\n\t"
108 "smulbb %0, %1, %2;\n"
109 : "=r"(res)
110 : "r"(a), "r"(b)
111 );
112 return res;
113 }
114 #define MULT16_16(a, b) (MULT16_16_armv5e(a, b))
116 #endif
