media/libyuv/source/row_mips.cc@b8a032363ba2
media/libyuv/source/row_mips.cc
Thu, 22 Jan 2015 13:21:57 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Thu, 22 Jan 2015 13:21:57 +0100
- branch
- TOR_BUG_9701
- changeset 15
- b8a032363ba2
- permissions
- -rw-r--r--
Incorporate requested changes from Mozilla in review:
https://bugzilla.mozilla.org/show_bug.cgi?id=1123480#c6
1 /*
2 * Copyright (c) 2012 The LibYuv project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
11 #include "libyuv/row.h"
13 #ifdef __cplusplus
14 namespace libyuv {
15 extern "C" {
16 #endif
18 // The following are available on Mips platforms:
19 #if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__)
21 #include <sgidefs.h>
23 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
24 #define HAS_MIPS_PREFETCH 1
25 #endif
27 #ifdef HAS_COPYROW_MIPS
28 void CopyRow_MIPS(const uint8* src, uint8* dst, int count) {
29 __asm__ __volatile__ (
30 ".set noreorder \n"
31 ".set noat \n"
32 "slti $at, %[count], 8 \n"
33 "bne $at ,$zero, $last8 \n"
34 "xor $t8, %[src], %[dst] \n"
35 "andi $t8, $t8, 0x3 \n"
37 "bne $t8, $zero, unaligned \n"
38 "negu $a3, %[dst] \n"
39 // make dst/src aligned
40 "andi $a3, $a3, 0x3 \n"
41 "beq $a3, $zero, $chk16w \n"
42 // word-aligned now count is the remining bytes count
43 "subu %[count], %[count], $a3 \n"
45 "lwr $t8, 0(%[src]) \n"
46 "addu %[src], %[src], $a3 \n"
47 "swr $t8, 0(%[dst]) \n"
48 "addu %[dst], %[dst], $a3 \n"
50 // Now the dst/src are mutually word-aligned with word-aligned addresses
51 "$chk16w: \n"
52 "andi $t8, %[count], 0x3f \n" // whole 64-B chunks?
53 // t8 is the byte count after 64-byte chunks
54 "beq %[count], $t8, chk8w \n"
55 // There will be at most 1 32-byte chunk after it
56 "subu $a3, %[count], $t8 \n" // the reminder
57 // Here a3 counts bytes in 16w chunks
58 "addu $a3, %[dst], $a3 \n"
59 // Now a3 is the final dst after 64-byte chunks
60 "addu $t0, %[dst], %[count] \n"
61 // t0 is the "past the end" address
63 // When in the loop we exercise "pref 30,x(a1)", the a1+x should not be past
64 // the "t0-32" address
65 // This means: for x=128 the last "safe" a1 address is "t0-160"
66 // Alternatively, for x=64 the last "safe" a1 address is "t0-96"
67 // we will use "pref 30,128(a1)", so "t0-160" is the limit
68 "subu $t9, $t0, 160 \n"
69 #ifdef HAS_MIPS_PREFETCH
70 // t9 is the "last safe pref 30,128(a1)" address
71 "pref 0, 0(%[src]) \n" // first line of src
72 "pref 0, 32(%[src]) \n" // second line of src
73 "pref 0, 64(%[src]) \n"
74 "pref 30, 32(%[dst]) \n"
75 #endif
76 // In case the a1 > t9 don't use "pref 30" at all
77 "sgtu $v1, %[dst], $t9 \n"
78 "bgtz $v1, $loop16w \n"
79 "nop \n"
80 // otherwise, start with using pref30
81 #ifdef HAS_MIPS_PREFETCH
82 "pref 30, 64(%[dst]) \n"
83 #endif
84 "$loop16w: \n"
85 #ifdef HAS_MIPS_PREFETCH
86 "pref 0, 96(%[src]) \n"
87 #endif
88 "lw $t0, 0(%[src]) \n"
89 "bgtz $v1, $skip_pref30_96 \n" // skip
90 "lw $t1, 4(%[src]) \n"
91 #ifdef HAS_MIPS_PREFETCH
92 "pref 30, 96(%[dst]) \n" // continue
93 #endif
94 "$skip_pref30_96: \n"
95 "lw $t2, 8(%[src]) \n"
96 "lw $t3, 12(%[src]) \n"
97 "lw $t4, 16(%[src]) \n"
98 "lw $t5, 20(%[src]) \n"
99 "lw $t6, 24(%[src]) \n"
100 "lw $t7, 28(%[src]) \n"
101 #ifdef HAS_MIPS_PREFETCH
102 "pref 0, 128(%[src]) \n"
103 #endif
104 // bring the next lines of src, addr 128
105 "sw $t0, 0(%[dst]) \n"
106 "sw $t1, 4(%[dst]) \n"
107 "sw $t2, 8(%[dst]) \n"
108 "sw $t3, 12(%[dst]) \n"
109 "sw $t4, 16(%[dst]) \n"
110 "sw $t5, 20(%[dst]) \n"
111 "sw $t6, 24(%[dst]) \n"
112 "sw $t7, 28(%[dst]) \n"
113 "lw $t0, 32(%[src]) \n"
114 "bgtz $v1, $skip_pref30_128 \n" // skip pref 30,128(a1)
115 "lw $t1, 36(%[src]) \n"
116 #ifdef HAS_MIPS_PREFETCH
117 "pref 30, 128(%[dst]) \n" // set dest, addr 128
118 #endif
119 "$skip_pref30_128: \n"
120 "lw $t2, 40(%[src]) \n"
121 "lw $t3, 44(%[src]) \n"
122 "lw $t4, 48(%[src]) \n"
123 "lw $t5, 52(%[src]) \n"
124 "lw $t6, 56(%[src]) \n"
125 "lw $t7, 60(%[src]) \n"
126 #ifdef HAS_MIPS_PREFETCH
127 "pref 0, 160(%[src]) \n"
128 #endif
129 // bring the next lines of src, addr 160
130 "sw $t0, 32(%[dst]) \n"
131 "sw $t1, 36(%[dst]) \n"
132 "sw $t2, 40(%[dst]) \n"
133 "sw $t3, 44(%[dst]) \n"
134 "sw $t4, 48(%[dst]) \n"
135 "sw $t5, 52(%[dst]) \n"
136 "sw $t6, 56(%[dst]) \n"
137 "sw $t7, 60(%[dst]) \n"
139 "addiu %[dst], %[dst], 64 \n" // adding 64 to dest
140 "sgtu $v1, %[dst], $t9 \n"
141 "bne %[dst], $a3, $loop16w \n"
142 " addiu %[src], %[src], 64 \n" // adding 64 to src
143 "move %[count], $t8 \n"
145 // Here we have src and dest word-aligned but less than 64-bytes to go
147 "chk8w: \n"
148 #ifdef HAS_MIPS_PREFETCH
149 "pref 0, 0x0(%[src]) \n"
150 #endif
151 "andi $t8, %[count], 0x1f \n" // 32-byte chunk?
152 // the t8 is the reminder count past 32-bytes
153 "beq %[count], $t8, chk1w \n"
154 // count=t8,no 32-byte chunk
155 " nop \n"
157 "lw $t0, 0(%[src]) \n"
158 "lw $t1, 4(%[src]) \n"
159 "lw $t2, 8(%[src]) \n"
160 "lw $t3, 12(%[src]) \n"
161 "lw $t4, 16(%[src]) \n"
162 "lw $t5, 20(%[src]) \n"
163 "lw $t6, 24(%[src]) \n"
164 "lw $t7, 28(%[src]) \n"
165 "addiu %[src], %[src], 32 \n"
167 "sw $t0, 0(%[dst]) \n"
168 "sw $t1, 4(%[dst]) \n"
169 "sw $t2, 8(%[dst]) \n"
170 "sw $t3, 12(%[dst]) \n"
171 "sw $t4, 16(%[dst]) \n"
172 "sw $t5, 20(%[dst]) \n"
173 "sw $t6, 24(%[dst]) \n"
174 "sw $t7, 28(%[dst]) \n"
175 "addiu %[dst], %[dst], 32 \n"
177 "chk1w: \n"
178 "andi %[count], $t8, 0x3 \n"
179 // now count is the reminder past 1w chunks
180 "beq %[count], $t8, $last8 \n"
181 " subu $a3, $t8, %[count] \n"
182 // a3 is count of bytes in 1w chunks
183 "addu $a3, %[dst], $a3 \n"
184 // now a3 is the dst address past the 1w chunks
185 // copying in words (4-byte chunks)
186 "$wordCopy_loop: \n"
187 "lw $t3, 0(%[src]) \n"
188 // the first t3 may be equal t0 ... optimize?
189 "addiu %[src], %[src],4 \n"
190 "addiu %[dst], %[dst],4 \n"
191 "bne %[dst], $a3,$wordCopy_loop \n"
192 " sw $t3, -4(%[dst]) \n"
194 // For the last (<8) bytes
195 "$last8: \n"
196 "blez %[count], leave \n"
197 " addu $a3, %[dst], %[count] \n" // a3 -last dst address
198 "$last8loop: \n"
199 "lb $v1, 0(%[src]) \n"
200 "addiu %[src], %[src], 1 \n"
201 "addiu %[dst], %[dst], 1 \n"
202 "bne %[dst], $a3, $last8loop \n"
203 " sb $v1, -1(%[dst]) \n"
205 "leave: \n"
206 " j $ra \n"
207 " nop \n"
209 //
210 // UNALIGNED case
211 //
213 "unaligned: \n"
214 // got here with a3="negu a1"
215 "andi $a3, $a3, 0x3 \n" // a1 is word aligned?
216 "beqz $a3, $ua_chk16w \n"
217 " subu %[count], %[count], $a3 \n"
218 // bytes left after initial a3 bytes
219 "lwr $v1, 0(%[src]) \n"
220 "lwl $v1, 3(%[src]) \n"
221 "addu %[src], %[src], $a3 \n" // a3 may be 1, 2 or 3
222 "swr $v1, 0(%[dst]) \n"
223 "addu %[dst], %[dst], $a3 \n"
224 // below the dst will be word aligned (NOTE1)
225 "$ua_chk16w: \n"
226 "andi $t8, %[count], 0x3f \n" // whole 64-B chunks?
227 // t8 is the byte count after 64-byte chunks
228 "beq %[count], $t8, ua_chk8w \n"
229 // if a2==t8, no 64-byte chunks
230 // There will be at most 1 32-byte chunk after it
231 "subu $a3, %[count], $t8 \n" // the reminder
232 // Here a3 counts bytes in 16w chunks
233 "addu $a3, %[dst], $a3 \n"
234 // Now a3 is the final dst after 64-byte chunks
235 "addu $t0, %[dst], %[count] \n" // t0 "past the end"
236 "subu $t9, $t0, 160 \n"
237 // t9 is the "last safe pref 30,128(a1)" address
238 #ifdef HAS_MIPS_PREFETCH
239 "pref 0, 0(%[src]) \n" // first line of src
240 "pref 0, 32(%[src]) \n" // second line addr 32
241 "pref 0, 64(%[src]) \n"
242 "pref 30, 32(%[dst]) \n"
243 #endif
244 // safe, as we have at least 64 bytes ahead
245 // In case the a1 > t9 don't use "pref 30" at all
246 "sgtu $v1, %[dst], $t9 \n"
247 "bgtz $v1, $ua_loop16w \n"
248 // skip "pref 30,64(a1)" for too short arrays
249 " nop \n"
250 // otherwise, start with using pref30
251 #ifdef HAS_MIPS_PREFETCH
252 "pref 30, 64(%[dst]) \n"
253 #endif
254 "$ua_loop16w: \n"
255 #ifdef HAS_MIPS_PREFETCH
256 "pref 0, 96(%[src]) \n"
257 #endif
258 "lwr $t0, 0(%[src]) \n"
259 "lwl $t0, 3(%[src]) \n"
260 "lwr $t1, 4(%[src]) \n"
261 "bgtz $v1, $ua_skip_pref30_96 \n"
262 " lwl $t1, 7(%[src]) \n"
263 #ifdef HAS_MIPS_PREFETCH
264 "pref 30, 96(%[dst]) \n"
265 #endif
266 // continue setting up the dest, addr 96
267 "$ua_skip_pref30_96: \n"
268 "lwr $t2, 8(%[src]) \n"
269 "lwl $t2, 11(%[src]) \n"
270 "lwr $t3, 12(%[src]) \n"
271 "lwl $t3, 15(%[src]) \n"
272 "lwr $t4, 16(%[src]) \n"
273 "lwl $t4, 19(%[src]) \n"
274 "lwr $t5, 20(%[src]) \n"
275 "lwl $t5, 23(%[src]) \n"
276 "lwr $t6, 24(%[src]) \n"
277 "lwl $t6, 27(%[src]) \n"
278 "lwr $t7, 28(%[src]) \n"
279 "lwl $t7, 31(%[src]) \n"
280 #ifdef HAS_MIPS_PREFETCH
281 "pref 0, 128(%[src]) \n"
282 #endif
283 // bring the next lines of src, addr 128
284 "sw $t0, 0(%[dst]) \n"
285 "sw $t1, 4(%[dst]) \n"
286 "sw $t2, 8(%[dst]) \n"
287 "sw $t3, 12(%[dst]) \n"
288 "sw $t4, 16(%[dst]) \n"
289 "sw $t5, 20(%[dst]) \n"
290 "sw $t6, 24(%[dst]) \n"
291 "sw $t7, 28(%[dst]) \n"
292 "lwr $t0, 32(%[src]) \n"
293 "lwl $t0, 35(%[src]) \n"
294 "lwr $t1, 36(%[src]) \n"
295 "bgtz $v1, ua_skip_pref30_128 \n"
296 " lwl $t1, 39(%[src]) \n"
297 #ifdef HAS_MIPS_PREFETCH
298 "pref 30, 128(%[dst]) \n"
299 #endif
300 // continue setting up the dest, addr 128
301 "ua_skip_pref30_128: \n"
303 "lwr $t2, 40(%[src]) \n"
304 "lwl $t2, 43(%[src]) \n"
305 "lwr $t3, 44(%[src]) \n"
306 "lwl $t3, 47(%[src]) \n"
307 "lwr $t4, 48(%[src]) \n"
308 "lwl $t4, 51(%[src]) \n"
309 "lwr $t5, 52(%[src]) \n"
310 "lwl $t5, 55(%[src]) \n"
311 "lwr $t6, 56(%[src]) \n"
312 "lwl $t6, 59(%[src]) \n"
313 "lwr $t7, 60(%[src]) \n"
314 "lwl $t7, 63(%[src]) \n"
315 #ifdef HAS_MIPS_PREFETCH
316 "pref 0, 160(%[src]) \n"
317 #endif
318 // bring the next lines of src, addr 160
319 "sw $t0, 32(%[dst]) \n"
320 "sw $t1, 36(%[dst]) \n"
321 "sw $t2, 40(%[dst]) \n"
322 "sw $t3, 44(%[dst]) \n"
323 "sw $t4, 48(%[dst]) \n"
324 "sw $t5, 52(%[dst]) \n"
325 "sw $t6, 56(%[dst]) \n"
326 "sw $t7, 60(%[dst]) \n"
328 "addiu %[dst],%[dst],64 \n" // adding 64 to dest
329 "sgtu $v1,%[dst],$t9 \n"
330 "bne %[dst],$a3,$ua_loop16w \n"
331 " addiu %[src],%[src],64 \n" // adding 64 to src
332 "move %[count],$t8 \n"
334 // Here we have src and dest word-aligned but less than 64-bytes to go
336 "ua_chk8w: \n"
337 #ifdef HAS_MIPS_PREFETCH
338 "pref 0, 0x0(%[src]) \n"
339 #endif
340 "andi $t8, %[count], 0x1f \n" // 32-byte chunk?
341 // the t8 is the reminder count
342 "beq %[count], $t8, $ua_chk1w \n"
343 // when count==t8, no 32-byte chunk
345 "lwr $t0, 0(%[src]) \n"
346 "lwl $t0, 3(%[src]) \n"
347 "lwr $t1, 4(%[src]) \n"
348 "lwl $t1, 7(%[src]) \n"
349 "lwr $t2, 8(%[src]) \n"
350 "lwl $t2, 11(%[src]) \n"
351 "lwr $t3, 12(%[src]) \n"
352 "lwl $t3, 15(%[src]) \n"
353 "lwr $t4, 16(%[src]) \n"
354 "lwl $t4, 19(%[src]) \n"
355 "lwr $t5, 20(%[src]) \n"
356 "lwl $t5, 23(%[src]) \n"
357 "lwr $t6, 24(%[src]) \n"
358 "lwl $t6, 27(%[src]) \n"
359 "lwr $t7, 28(%[src]) \n"
360 "lwl $t7, 31(%[src]) \n"
361 "addiu %[src], %[src], 32 \n"
363 "sw $t0, 0(%[dst]) \n"
364 "sw $t1, 4(%[dst]) \n"
365 "sw $t2, 8(%[dst]) \n"
366 "sw $t3, 12(%[dst]) \n"
367 "sw $t4, 16(%[dst]) \n"
368 "sw $t5, 20(%[dst]) \n"
369 "sw $t6, 24(%[dst]) \n"
370 "sw $t7, 28(%[dst]) \n"
371 "addiu %[dst], %[dst], 32 \n"
373 "$ua_chk1w: \n"
374 "andi %[count], $t8, 0x3 \n"
375 // now count is the reminder past 1w chunks
376 "beq %[count], $t8, ua_smallCopy \n"
377 "subu $a3, $t8, %[count] \n"
378 // a3 is count of bytes in 1w chunks
379 "addu $a3, %[dst], $a3 \n"
380 // now a3 is the dst address past the 1w chunks
382 // copying in words (4-byte chunks)
383 "$ua_wordCopy_loop: \n"
384 "lwr $v1, 0(%[src]) \n"
385 "lwl $v1, 3(%[src]) \n"
386 "addiu %[src], %[src], 4 \n"
387 "addiu %[dst], %[dst], 4 \n"
388 // note: dst=a1 is word aligned here, see NOTE1
389 "bne %[dst], $a3, $ua_wordCopy_loop \n"
390 " sw $v1,-4(%[dst]) \n"
392 // Now less than 4 bytes (value in count) left to copy
393 "ua_smallCopy: \n"
394 "beqz %[count], leave \n"
395 " addu $a3, %[dst], %[count] \n" // a3 = last dst address
396 "$ua_smallCopy_loop: \n"
397 "lb $v1, 0(%[src]) \n"
398 "addiu %[src], %[src], 1 \n"
399 "addiu %[dst], %[dst], 1 \n"
400 "bne %[dst],$a3,$ua_smallCopy_loop \n"
401 " sb $v1, -1(%[dst]) \n"
403 "j $ra \n"
404 " nop \n"
405 ".set at \n"
406 ".set reorder \n"
407 : [dst] "+r" (dst), [src] "+r" (src)
408 : [count] "r" (count)
409 : "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
410 "t8", "t9", "a3", "v1", "at"
411 );
412 }
413 #endif // HAS_COPYROW_MIPS
415 // MIPS DSPR2 functions
416 #if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips_dsp) && \
417 (__mips_dsp_rev >= 2)
418 void SplitUVRow_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
419 int width) {
420 __asm__ __volatile__ (
421 ".set push \n"
422 ".set noreorder \n"
423 "srl $t4, %[width], 4 \n" // multiplies of 16
424 "blez $t4, 2f \n"
425 " andi %[width], %[width], 0xf \n" // residual
427 ".p2align 2 \n"
428 "1: \n"
429 "addiu $t4, $t4, -1 \n"
430 "lw $t0, 0(%[src_uv]) \n" // V1 | U1 | V0 | U0
431 "lw $t1, 4(%[src_uv]) \n" // V3 | U3 | V2 | U2
432 "lw $t2, 8(%[src_uv]) \n" // V5 | U5 | V4 | U4
433 "lw $t3, 12(%[src_uv]) \n" // V7 | U7 | V6 | U6
434 "lw $t5, 16(%[src_uv]) \n" // V9 | U9 | V8 | U8
435 "lw $t6, 20(%[src_uv]) \n" // V11 | U11 | V10 | U10
436 "lw $t7, 24(%[src_uv]) \n" // V13 | U13 | V12 | U12
437 "lw $t8, 28(%[src_uv]) \n" // V15 | U15 | V14 | U14
438 "addiu %[src_uv], %[src_uv], 32 \n"
439 "precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
440 "precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
441 "precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
442 "precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
443 "precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
444 "precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
445 "precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
446 "precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
447 "sw $t9, 0(%[dst_v]) \n"
448 "sw $t0, 0(%[dst_u]) \n"
449 "sw $t1, 4(%[dst_v]) \n"
450 "sw $t2, 4(%[dst_u]) \n"
451 "sw $t3, 8(%[dst_v]) \n"
452 "sw $t5, 8(%[dst_u]) \n"
453 "sw $t6, 12(%[dst_v]) \n"
454 "sw $t7, 12(%[dst_u]) \n"
455 "addiu %[dst_v], %[dst_v], 16 \n"
456 "bgtz $t4, 1b \n"
457 " addiu %[dst_u], %[dst_u], 16 \n"
459 "beqz %[width], 3f \n"
460 " nop \n"
462 "2: \n"
463 "lbu $t0, 0(%[src_uv]) \n"
464 "lbu $t1, 1(%[src_uv]) \n"
465 "addiu %[src_uv], %[src_uv], 2 \n"
466 "addiu %[width], %[width], -1 \n"
467 "sb $t0, 0(%[dst_u]) \n"
468 "sb $t1, 0(%[dst_v]) \n"
469 "addiu %[dst_u], %[dst_u], 1 \n"
470 "bgtz %[width], 2b \n"
471 " addiu %[dst_v], %[dst_v], 1 \n"
473 "3: \n"
474 ".set pop \n"
475 : [src_uv] "+r" (src_uv),
476 [width] "+r" (width),
477 [dst_u] "+r" (dst_u),
478 [dst_v] "+r" (dst_v)
479 :
480 : "t0", "t1", "t2", "t3",
481 "t4", "t5", "t6", "t7", "t8", "t9"
482 );
483 }
485 void SplitUVRow_Unaligned_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u,
486 uint8* dst_v, int width) {
487 __asm__ __volatile__ (
488 ".set push \n"
489 ".set noreorder \n"
490 "srl $t4, %[width], 4 \n" // multiplies of 16
491 "blez $t4, 2f \n"
492 " andi %[width], %[width], 0xf \n" // residual
494 ".p2align 2 \n"
495 "1: \n"
496 "addiu $t4, $t4, -1 \n"
497 "lwr $t0, 0(%[src_uv]) \n"
498 "lwl $t0, 3(%[src_uv]) \n" // V1 | U1 | V0 | U0
499 "lwr $t1, 4(%[src_uv]) \n"
500 "lwl $t1, 7(%[src_uv]) \n" // V3 | U3 | V2 | U2
501 "lwr $t2, 8(%[src_uv]) \n"
502 "lwl $t2, 11(%[src_uv]) \n" // V5 | U5 | V4 | U4
503 "lwr $t3, 12(%[src_uv]) \n"
504 "lwl $t3, 15(%[src_uv]) \n" // V7 | U7 | V6 | U6
505 "lwr $t5, 16(%[src_uv]) \n"
506 "lwl $t5, 19(%[src_uv]) \n" // V9 | U9 | V8 | U8
507 "lwr $t6, 20(%[src_uv]) \n"
508 "lwl $t6, 23(%[src_uv]) \n" // V11 | U11 | V10 | U10
509 "lwr $t7, 24(%[src_uv]) \n"
510 "lwl $t7, 27(%[src_uv]) \n" // V13 | U13 | V12 | U12
511 "lwr $t8, 28(%[src_uv]) \n"
512 "lwl $t8, 31(%[src_uv]) \n" // V15 | U15 | V14 | U14
513 "precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
514 "precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
515 "precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
516 "precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
517 "precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
518 "precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
519 "precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
520 "precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
521 "addiu %[src_uv], %[src_uv], 32 \n"
522 "swr $t9, 0(%[dst_v]) \n"
523 "swl $t9, 3(%[dst_v]) \n"
524 "swr $t0, 0(%[dst_u]) \n"
525 "swl $t0, 3(%[dst_u]) \n"
526 "swr $t1, 4(%[dst_v]) \n"
527 "swl $t1, 7(%[dst_v]) \n"
528 "swr $t2, 4(%[dst_u]) \n"
529 "swl $t2, 7(%[dst_u]) \n"
530 "swr $t3, 8(%[dst_v]) \n"
531 "swl $t3, 11(%[dst_v]) \n"
532 "swr $t5, 8(%[dst_u]) \n"
533 "swl $t5, 11(%[dst_u]) \n"
534 "swr $t6, 12(%[dst_v]) \n"
535 "swl $t6, 15(%[dst_v]) \n"
536 "swr $t7, 12(%[dst_u]) \n"
537 "swl $t7, 15(%[dst_u]) \n"
538 "addiu %[dst_u], %[dst_u], 16 \n"
539 "bgtz $t4, 1b \n"
540 " addiu %[dst_v], %[dst_v], 16 \n"
542 "beqz %[width], 3f \n"
543 " nop \n"
545 "2: \n"
546 "lbu $t0, 0(%[src_uv]) \n"
547 "lbu $t1, 1(%[src_uv]) \n"
548 "addiu %[src_uv], %[src_uv], 2 \n"
549 "addiu %[width], %[width], -1 \n"
550 "sb $t0, 0(%[dst_u]) \n"
551 "sb $t1, 0(%[dst_v]) \n"
552 "addiu %[dst_u], %[dst_u], 1 \n"
553 "bgtz %[width], 2b \n"
554 " addiu %[dst_v], %[dst_v], 1 \n"
556 "3: \n"
557 ".set pop \n"
558 : [src_uv] "+r" (src_uv),
559 [width] "+r" (width),
560 [dst_u] "+r" (dst_u),
561 [dst_v] "+r" (dst_v)
562 :
563 : "t0", "t1", "t2", "t3",
564 "t4", "t5", "t6", "t7", "t8", "t9"
565 );
566 }
568 void MirrorRow_MIPS_DSPR2(const uint8* src, uint8* dst, int width) {
569 __asm__ __volatile__ (
570 ".set push \n"
571 ".set noreorder \n"
573 "srl $t4, %[width], 4 \n" // multiplies of 16
574 "andi $t5, %[width], 0xf \n"
575 "blez $t4, 2f \n"
576 " addu %[src], %[src], %[width] \n" // src += width
578 ".p2align 2 \n"
579 "1: \n"
580 "lw $t0, -16(%[src]) \n" // |3|2|1|0|
581 "lw $t1, -12(%[src]) \n" // |7|6|5|4|
582 "lw $t2, -8(%[src]) \n" // |11|10|9|8|
583 "lw $t3, -4(%[src]) \n" // |15|14|13|12|
584 "wsbh $t0, $t0 \n" // |2|3|0|1|
585 "wsbh $t1, $t1 \n" // |6|7|4|5|
586 "wsbh $t2, $t2 \n" // |10|11|8|9|
587 "wsbh $t3, $t3 \n" // |14|15|12|13|
588 "rotr $t0, $t0, 16 \n" // |0|1|2|3|
589 "rotr $t1, $t1, 16 \n" // |4|5|6|7|
590 "rotr $t2, $t2, 16 \n" // |8|9|10|11|
591 "rotr $t3, $t3, 16 \n" // |12|13|14|15|
592 "addiu %[src], %[src], -16 \n"
593 "addiu $t4, $t4, -1 \n"
594 "sw $t3, 0(%[dst]) \n" // |15|14|13|12|
595 "sw $t2, 4(%[dst]) \n" // |11|10|9|8|
596 "sw $t1, 8(%[dst]) \n" // |7|6|5|4|
597 "sw $t0, 12(%[dst]) \n" // |3|2|1|0|
598 "bgtz $t4, 1b \n"
599 " addiu %[dst], %[dst], 16 \n"
600 "beqz $t5, 3f \n"
601 " nop \n"
603 "2: \n"
604 "lbu $t0, -1(%[src]) \n"
605 "addiu $t5, $t5, -1 \n"
606 "addiu %[src], %[src], -1 \n"
607 "sb $t0, 0(%[dst]) \n"
608 "bgez $t5, 2b \n"
609 " addiu %[dst], %[dst], 1 \n"
611 "3: \n"
612 ".set pop \n"
613 : [src] "+r" (src), [dst] "+r" (dst)
614 : [width] "r" (width)
615 : "t0", "t1", "t2", "t3", "t4", "t5"
616 );
617 }
619 void MirrorUVRow_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
620 int width) {
621 int x = 0;
622 int y = 0;
623 __asm__ __volatile__ (
624 ".set push \n"
625 ".set noreorder \n"
627 "addu $t4, %[width], %[width] \n"
628 "srl %[x], %[width], 4 \n"
629 "andi %[y], %[width], 0xf \n"
630 "blez %[x], 2f \n"
631 " addu %[src_uv], %[src_uv], $t4 \n"
633 ".p2align 2 \n"
634 "1: \n"
635 "lw $t0, -32(%[src_uv]) \n" // |3|2|1|0|
636 "lw $t1, -28(%[src_uv]) \n" // |7|6|5|4|
637 "lw $t2, -24(%[src_uv]) \n" // |11|10|9|8|
638 "lw $t3, -20(%[src_uv]) \n" // |15|14|13|12|
639 "lw $t4, -16(%[src_uv]) \n" // |19|18|17|16|
640 "lw $t6, -12(%[src_uv]) \n" // |23|22|21|20|
641 "lw $t7, -8(%[src_uv]) \n" // |27|26|25|24|
642 "lw $t8, -4(%[src_uv]) \n" // |31|30|29|28|
644 "rotr $t0, $t0, 16 \n" // |1|0|3|2|
645 "rotr $t1, $t1, 16 \n" // |5|4|7|6|
646 "rotr $t2, $t2, 16 \n" // |9|8|11|10|
647 "rotr $t3, $t3, 16 \n" // |13|12|15|14|
648 "rotr $t4, $t4, 16 \n" // |17|16|19|18|
649 "rotr $t6, $t6, 16 \n" // |21|20|23|22|
650 "rotr $t7, $t7, 16 \n" // |25|24|27|26|
651 "rotr $t8, $t8, 16 \n" // |29|28|31|30|
652 "precr.qb.ph $t9, $t0, $t1 \n" // |0|2|4|6|
653 "precrq.qb.ph $t5, $t0, $t1 \n" // |1|3|5|7|
654 "precr.qb.ph $t0, $t2, $t3 \n" // |8|10|12|14|
655 "precrq.qb.ph $t1, $t2, $t3 \n" // |9|11|13|15|
656 "precr.qb.ph $t2, $t4, $t6 \n" // |16|18|20|22|
657 "precrq.qb.ph $t3, $t4, $t6 \n" // |17|19|21|23|
658 "precr.qb.ph $t4, $t7, $t8 \n" // |24|26|28|30|
659 "precrq.qb.ph $t6, $t7, $t8 \n" // |25|27|29|31|
660 "addiu %[src_uv], %[src_uv], -32 \n"
661 "addiu %[x], %[x], -1 \n"
662 "swr $t4, 0(%[dst_u]) \n"
663 "swl $t4, 3(%[dst_u]) \n" // |30|28|26|24|
664 "swr $t6, 0(%[dst_v]) \n"
665 "swl $t6, 3(%[dst_v]) \n" // |31|29|27|25|
666 "swr $t2, 4(%[dst_u]) \n"
667 "swl $t2, 7(%[dst_u]) \n" // |22|20|18|16|
668 "swr $t3, 4(%[dst_v]) \n"
669 "swl $t3, 7(%[dst_v]) \n" // |23|21|19|17|
670 "swr $t0, 8(%[dst_u]) \n"
671 "swl $t0, 11(%[dst_u]) \n" // |14|12|10|8|
672 "swr $t1, 8(%[dst_v]) \n"
673 "swl $t1, 11(%[dst_v]) \n" // |15|13|11|9|
674 "swr $t9, 12(%[dst_u]) \n"
675 "swl $t9, 15(%[dst_u]) \n" // |6|4|2|0|
676 "swr $t5, 12(%[dst_v]) \n"
677 "swl $t5, 15(%[dst_v]) \n" // |7|5|3|1|
678 "addiu %[dst_v], %[dst_v], 16 \n"
679 "bgtz %[x], 1b \n"
680 " addiu %[dst_u], %[dst_u], 16 \n"
681 "beqz %[y], 3f \n"
682 " nop \n"
683 "b 2f \n"
684 " nop \n"
686 "2: \n"
687 "lbu $t0, -2(%[src_uv]) \n"
688 "lbu $t1, -1(%[src_uv]) \n"
689 "addiu %[src_uv], %[src_uv], -2 \n"
690 "addiu %[y], %[y], -1 \n"
691 "sb $t0, 0(%[dst_u]) \n"
692 "sb $t1, 0(%[dst_v]) \n"
693 "addiu %[dst_u], %[dst_u], 1 \n"
694 "bgtz %[y], 2b \n"
695 " addiu %[dst_v], %[dst_v], 1 \n"
697 "3: \n"
698 ".set pop \n"
699 : [src_uv] "+r" (src_uv),
700 [dst_u] "+r" (dst_u),
701 [dst_v] "+r" (dst_v),
702 [x] "=&r" (x),
703 [y] "+r" (y)
704 : [width] "r" (width)
705 : "t0", "t1", "t2", "t3", "t4",
706 "t5", "t7", "t8", "t9"
707 );
708 }
710 // Convert (4 Y and 2 VU) I422 and arrange RGB values into
711 // t5 = | 0 | B0 | 0 | b0 |
712 // t4 = | 0 | B1 | 0 | b1 |
713 // t9 = | 0 | G0 | 0 | g0 |
714 // t8 = | 0 | G1 | 0 | g1 |
715 // t2 = | 0 | R0 | 0 | r0 |
716 // t1 = | 0 | R1 | 0 | r1 |
717 #define I422ToTransientMipsRGB \
718 "lw $t0, 0(%[y_buf]) \n" \
719 "lhu $t1, 0(%[u_buf]) \n" \
720 "lhu $t2, 0(%[v_buf]) \n" \
721 "preceu.ph.qbr $t1, $t1 \n" \
722 "preceu.ph.qbr $t2, $t2 \n" \
723 "preceu.ph.qbra $t3, $t0 \n" \
724 "preceu.ph.qbla $t0, $t0 \n" \
725 "subu.ph $t1, $t1, $s5 \n" \
726 "subu.ph $t2, $t2, $s5 \n" \
727 "subu.ph $t3, $t3, $s4 \n" \
728 "subu.ph $t0, $t0, $s4 \n" \
729 "mul.ph $t3, $t3, $s0 \n" \
730 "mul.ph $t0, $t0, $s0 \n" \
731 "shll.ph $t4, $t1, 0x7 \n" \
732 "subu.ph $t4, $t4, $t1 \n" \
733 "mul.ph $t6, $t1, $s1 \n" \
734 "mul.ph $t1, $t2, $s2 \n" \
735 "addq_s.ph $t5, $t4, $t3 \n" \
736 "addq_s.ph $t4, $t4, $t0 \n" \
737 "shra.ph $t5, $t5, 6 \n" \
738 "shra.ph $t4, $t4, 6 \n" \
739 "addiu %[u_buf], 2 \n" \
740 "addiu %[v_buf], 2 \n" \
741 "addu.ph $t6, $t6, $t1 \n" \
742 "mul.ph $t1, $t2, $s3 \n" \
743 "addu.ph $t9, $t6, $t3 \n" \
744 "addu.ph $t8, $t6, $t0 \n" \
745 "shra.ph $t9, $t9, 6 \n" \
746 "shra.ph $t8, $t8, 6 \n" \
747 "addu.ph $t2, $t1, $t3 \n" \
748 "addu.ph $t1, $t1, $t0 \n" \
749 "shra.ph $t2, $t2, 6 \n" \
750 "shra.ph $t1, $t1, 6 \n" \
751 "subu.ph $t5, $t5, $s5 \n" \
752 "subu.ph $t4, $t4, $s5 \n" \
753 "subu.ph $t9, $t9, $s5 \n" \
754 "subu.ph $t8, $t8, $s5 \n" \
755 "subu.ph $t2, $t2, $s5 \n" \
756 "subu.ph $t1, $t1, $s5 \n" \
757 "shll_s.ph $t5, $t5, 8 \n" \
758 "shll_s.ph $t4, $t4, 8 \n" \
759 "shll_s.ph $t9, $t9, 8 \n" \
760 "shll_s.ph $t8, $t8, 8 \n" \
761 "shll_s.ph $t2, $t2, 8 \n" \
762 "shll_s.ph $t1, $t1, 8 \n" \
763 "shra.ph $t5, $t5, 8 \n" \
764 "shra.ph $t4, $t4, 8 \n" \
765 "shra.ph $t9, $t9, 8 \n" \
766 "shra.ph $t8, $t8, 8 \n" \
767 "shra.ph $t2, $t2, 8 \n" \
768 "shra.ph $t1, $t1, 8 \n" \
769 "addu.ph $t5, $t5, $s5 \n" \
770 "addu.ph $t4, $t4, $s5 \n" \
771 "addu.ph $t9, $t9, $s5 \n" \
772 "addu.ph $t8, $t8, $s5 \n" \
773 "addu.ph $t2, $t2, $s5 \n" \
774 "addu.ph $t1, $t1, $s5 \n"
776 void I422ToARGBRow_MIPS_DSPR2(const uint8* y_buf,
777 const uint8* u_buf,
778 const uint8* v_buf,
779 uint8* rgb_buf,
780 int width) {
781 __asm__ __volatile__ (
782 ".set push \n"
783 ".set noreorder \n"
784 "beqz %[width], 2f \n"
785 " repl.ph $s0, 74 \n" // |YG|YG| = |74|74|
786 "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
787 "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
788 "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
789 "repl.ph $s4, 16 \n" // |0|16|0|16|
790 "repl.ph $s5, 128 \n" // |128|128| // clipping
791 "lui $s6, 0xff00 \n"
792 "ori $s6, 0xff00 \n" // |ff|00|ff|00|ff|
794 ".p2align 2 \n"
795 "1: \n"
796 I422ToTransientMipsRGB
797 // Arranging into argb format
798 "precr.qb.ph $t4, $t8, $t4 \n" // |G1|g1|B1|b1|
799 "precr.qb.ph $t5, $t9, $t5 \n" // |G0|g0|B0|b0|
800 "addiu %[width], -4 \n"
801 "precrq.qb.ph $t8, $t4, $t5 \n" // |G1|B1|G0|B0|
802 "precr.qb.ph $t9, $t4, $t5 \n" // |g1|b1|g0|b0|
803 "precr.qb.ph $t2, $t1, $t2 \n" // |R1|r1|R0|r0|
805 "addiu %[y_buf], 4 \n"
806 "preceu.ph.qbla $t1, $t2 \n" // |0 |R1|0 |R0|
807 "preceu.ph.qbra $t2, $t2 \n" // |0 |r1|0 |r0|
808 "or $t1, $t1, $s6 \n" // |ff|R1|ff|R0|
809 "or $t2, $t2, $s6 \n" // |ff|r1|ff|r0|
810 "precrq.ph.w $t0, $t2, $t9 \n" // |ff|r1|g1|b1|
811 "precrq.ph.w $t3, $t1, $t8 \n" // |ff|R1|G1|B1|
812 "sll $t9, $t9, 16 \n"
813 "sll $t8, $t8, 16 \n"
814 "packrl.ph $t2, $t2, $t9 \n" // |ff|r0|g0|b0|
815 "packrl.ph $t1, $t1, $t8 \n" // |ff|R0|G0|B0|
816 // Store results.
817 "sw $t2, 0(%[rgb_buf]) \n"
818 "sw $t0, 4(%[rgb_buf]) \n"
819 "sw $t1, 8(%[rgb_buf]) \n"
820 "sw $t3, 12(%[rgb_buf]) \n"
821 "bnez %[width], 1b \n"
822 " addiu %[rgb_buf], 16 \n"
823 "2: \n"
824 ".set pop \n"
825 :[y_buf] "+r" (y_buf),
826 [u_buf] "+r" (u_buf),
827 [v_buf] "+r" (v_buf),
828 [width] "+r" (width),
829 [rgb_buf] "+r" (rgb_buf)
830 :
831 : "t0", "t1", "t2", "t3", "t4", "t5",
832 "t6", "t7", "t8", "t9",
833 "s0", "s1", "s2", "s3",
834 "s4", "s5", "s6"
835 );
836 }
838 void I422ToABGRRow_MIPS_DSPR2(const uint8* y_buf,
839 const uint8* u_buf,
840 const uint8* v_buf,
841 uint8* rgb_buf,
842 int width) {
843 __asm__ __volatile__ (
844 ".set push \n"
845 ".set noreorder \n"
846 "beqz %[width], 2f \n"
847 " repl.ph $s0, 74 \n" // |YG|YG| = |74|74|
848 "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
849 "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
850 "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
851 "repl.ph $s4, 16 \n" // |0|16|0|16|
852 "repl.ph $s5, 128 \n" // |128|128|
853 "lui $s6, 0xff00 \n"
854 "ori $s6, 0xff00 \n" // |ff|00|ff|00|
856 ".p2align 2 \n"
857 "1: \n"
858 I422ToTransientMipsRGB
859 // Arranging into abgr format
860 "precr.qb.ph $t0, $t8, $t1 \n" // |G1|g1|R1|r1|
861 "precr.qb.ph $t3, $t9, $t2 \n" // |G0|g0|R0|r0|
862 "precrq.qb.ph $t8, $t0, $t3 \n" // |G1|R1|G0|R0|
863 "precr.qb.ph $t9, $t0, $t3 \n" // |g1|r1|g0|r0|
865 "precr.qb.ph $t2, $t4, $t5 \n" // |B1|b1|B0|b0|
866 "addiu %[width], -4 \n"
867 "addiu %[y_buf], 4 \n"
868 "preceu.ph.qbla $t1, $t2 \n" // |0 |B1|0 |B0|
869 "preceu.ph.qbra $t2, $t2 \n" // |0 |b1|0 |b0|
870 "or $t1, $t1, $s6 \n" // |ff|B1|ff|B0|
871 "or $t2, $t2, $s6 \n" // |ff|b1|ff|b0|
872 "precrq.ph.w $t0, $t2, $t9 \n" // |ff|b1|g1|r1|
873 "precrq.ph.w $t3, $t1, $t8 \n" // |ff|B1|G1|R1|
874 "sll $t9, $t9, 16 \n"
875 "sll $t8, $t8, 16 \n"
876 "packrl.ph $t2, $t2, $t9 \n" // |ff|b0|g0|r0|
877 "packrl.ph $t1, $t1, $t8 \n" // |ff|B0|G0|R0|
878 // Store results.
879 "sw $t2, 0(%[rgb_buf]) \n"
880 "sw $t0, 4(%[rgb_buf]) \n"
881 "sw $t1, 8(%[rgb_buf]) \n"
882 "sw $t3, 12(%[rgb_buf]) \n"
883 "bnez %[width], 1b \n"
884 " addiu %[rgb_buf], 16 \n"
885 "2: \n"
886 ".set pop \n"
887 :[y_buf] "+r" (y_buf),
888 [u_buf] "+r" (u_buf),
889 [v_buf] "+r" (v_buf),
890 [width] "+r" (width),
891 [rgb_buf] "+r" (rgb_buf)
892 :
893 : "t0", "t1", "t2", "t3", "t4", "t5",
894 "t6", "t7", "t8", "t9",
895 "s0", "s1", "s2", "s3",
896 "s4", "s5", "s6"
897 );
898 }
900 void I422ToBGRARow_MIPS_DSPR2(const uint8* y_buf,
901 const uint8* u_buf,
902 const uint8* v_buf,
903 uint8* rgb_buf,
904 int width) {
905 __asm__ __volatile__ (
906 ".set push \n"
907 ".set noreorder \n"
908 "beqz %[width], 2f \n"
909 " repl.ph $s0, 74 \n" // |YG|YG| = |74 |74 |
910 "repl.ph $s1, -25 \n" // |UG|UG| = |-25|-25|
911 "repl.ph $s2, -52 \n" // |VG|VG| = |-52|-52|
912 "repl.ph $s3, 102 \n" // |VR|VR| = |102|102|
913 "repl.ph $s4, 16 \n" // |0|16|0|16|
914 "repl.ph $s5, 128 \n" // |128|128|
915 "lui $s6, 0xff \n"
916 "ori $s6, 0xff \n" // |00|ff|00|ff|
918 ".p2align 2 \n"
919 "1: \n"
920 I422ToTransientMipsRGB
921 // Arranging into bgra format
922 "precr.qb.ph $t4, $t4, $t8 \n" // |B1|b1|G1|g1|
923 "precr.qb.ph $t5, $t5, $t9 \n" // |B0|b0|G0|g0|
924 "precrq.qb.ph $t8, $t4, $t5 \n" // |B1|G1|B0|G0|
925 "precr.qb.ph $t9, $t4, $t5 \n" // |b1|g1|b0|g0|
927 "precr.qb.ph $t2, $t1, $t2 \n" // |R1|r1|R0|r0|
928 "addiu %[width], -4 \n"
929 "addiu %[y_buf], 4 \n"
930 "preceu.ph.qbla $t1, $t2 \n" // |0 |R1|0 |R0|
931 "preceu.ph.qbra $t2, $t2 \n" // |0 |r1|0 |r0|
932 "sll $t1, $t1, 8 \n" // |R1|0 |R0|0 |
933 "sll $t2, $t2, 8 \n" // |r1|0 |r0|0 |
934 "or $t1, $t1, $s6 \n" // |R1|ff|R0|ff|
935 "or $t2, $t2, $s6 \n" // |r1|ff|r0|ff|
936 "precrq.ph.w $t0, $t9, $t2 \n" // |b1|g1|r1|ff|
937 "precrq.ph.w $t3, $t8, $t1 \n" // |B1|G1|R1|ff|
938 "sll $t1, $t1, 16 \n"
939 "sll $t2, $t2, 16 \n"
940 "packrl.ph $t2, $t9, $t2 \n" // |b0|g0|r0|ff|
941 "packrl.ph $t1, $t8, $t1 \n" // |B0|G0|R0|ff|
942 // Store results.
943 "sw $t2, 0(%[rgb_buf]) \n"
944 "sw $t0, 4(%[rgb_buf]) \n"
945 "sw $t1, 8(%[rgb_buf]) \n"
946 "sw $t3, 12(%[rgb_buf]) \n"
947 "bnez %[width], 1b \n"
948 " addiu %[rgb_buf], 16 \n"
949 "2: \n"
950 ".set pop \n"
951 :[y_buf] "+r" (y_buf),
952 [u_buf] "+r" (u_buf),
953 [v_buf] "+r" (v_buf),
954 [width] "+r" (width),
955 [rgb_buf] "+r" (rgb_buf)
956 :
957 : "t0", "t1", "t2", "t3", "t4", "t5",
958 "t6", "t7", "t8", "t9",
959 "s0", "s1", "s2", "s3",
960 "s4", "s5", "s6"
961 );
962 }
964 // Bilinear filter 8x2 -> 8x1
965 void InterpolateRows_MIPS_DSPR2(uint8* dst_ptr, const uint8* src_ptr,
966 ptrdiff_t src_stride, int dst_width,
967 int source_y_fraction) {
968 int y0_fraction = 256 - source_y_fraction;
969 const uint8* src_ptr1 = src_ptr + src_stride;
971 __asm__ __volatile__ (
972 ".set push \n"
973 ".set noreorder \n"
975 "replv.ph $t0, %[y0_fraction] \n"
976 "replv.ph $t1, %[source_y_fraction] \n"
978 ".p2align 2 \n"
979 "1: \n"
980 "lw $t2, 0(%[src_ptr]) \n"
981 "lw $t3, 0(%[src_ptr1]) \n"
982 "lw $t4, 4(%[src_ptr]) \n"
983 "lw $t5, 4(%[src_ptr1]) \n"
984 "muleu_s.ph.qbl $t6, $t2, $t0 \n"
985 "muleu_s.ph.qbr $t7, $t2, $t0 \n"
986 "muleu_s.ph.qbl $t8, $t3, $t1 \n"
987 "muleu_s.ph.qbr $t9, $t3, $t1 \n"
988 "muleu_s.ph.qbl $t2, $t4, $t0 \n"
989 "muleu_s.ph.qbr $t3, $t4, $t0 \n"
990 "muleu_s.ph.qbl $t4, $t5, $t1 \n"
991 "muleu_s.ph.qbr $t5, $t5, $t1 \n"
992 "addq.ph $t6, $t6, $t8 \n"
993 "addq.ph $t7, $t7, $t9 \n"
994 "addq.ph $t2, $t2, $t4 \n"
995 "addq.ph $t3, $t3, $t5 \n"
996 "shra.ph $t6, $t6, 8 \n"
997 "shra.ph $t7, $t7, 8 \n"
998 "shra.ph $t2, $t2, 8 \n"
999 "shra.ph $t3, $t3, 8 \n"
1000 "precr.qb.ph $t6, $t6, $t7 \n"
1001 "precr.qb.ph $t2, $t2, $t3 \n"
1002 "addiu %[src_ptr], %[src_ptr], 8 \n"
1003 "addiu %[src_ptr1], %[src_ptr1], 8 \n"
1004 "addiu %[dst_width], %[dst_width], -8 \n"
1005 "sw $t6, 0(%[dst_ptr]) \n"
1006 "sw $t2, 4(%[dst_ptr]) \n"
1007 "bgtz %[dst_width], 1b \n"
1008 " addiu %[dst_ptr], %[dst_ptr], 8 \n"
1010 ".set pop \n"
1011 : [dst_ptr] "+r" (dst_ptr),
1012 [src_ptr1] "+r" (src_ptr1),
1013 [src_ptr] "+r" (src_ptr),
1014 [dst_width] "+r" (dst_width)
1015 : [source_y_fraction] "r" (source_y_fraction),
1016 [y0_fraction] "r" (y0_fraction),
1017 [src_stride] "r" (src_stride)
1018 : "t0", "t1", "t2", "t3", "t4", "t5",
1019 "t6", "t7", "t8", "t9"
1020 );
1021 }
1022 #endif // __mips_dsp_rev >= 2
1024 #endif // defined(__mips__)
1026 #ifdef __cplusplus
1027 } // extern "C"
1028 } // namespace libyuv
1029 #endif
