The Tor Browser: security/sandbox/chromium/base/cpu.cc@b8a032363ba2

Incorporate requested changes from Mozilla in review:
https://bugzilla.mozilla.org/show_bug.cgi?id=1123480#c6

     1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.

     2 // Use of this source code is governed by a BSD-style license that can be

     3 // found in the LICENSE file.

     5 #include "base/cpu.h"

     7 #include <string.h>

     9 #include <algorithm>

    11 #include "build/build_config.h"

    13 #if defined(ARCH_CPU_X86_FAMILY)

    14 #if defined(_MSC_VER)

    15 #include <intrin.h>

    16 #endif

    17 #endif

    19 namespace base {

    21 CPU::CPU()

    22   : signature_(0),

    23     type_(0),

    24     family_(0),

    25     model_(0),

    26     stepping_(0),

    27     ext_model_(0),

    28     ext_family_(0),

    29     has_mmx_(false),

    30     has_sse_(false),

    31     has_sse2_(false),

    32     has_sse3_(false),

    33     has_ssse3_(false),

    34     has_sse41_(false),

    35     has_sse42_(false),

    36     has_non_stop_time_stamp_counter_(false),

    37     cpu_vendor_("unknown") {

    38   Initialize();

    39 }

    41 #if defined(ARCH_CPU_X86_FAMILY)

    42 #ifndef _MSC_VER

    44 #if defined(__pic__) && defined(__i386__)

    46 void __cpuid(int cpu_info[4], int info_type) {

    47   __asm__ volatile (

    48     "mov %%ebx, %%edi\n"

    49     "cpuid\n"

    50     "xchg %%edi, %%ebx\n"

    51     : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])

    52     : "a"(info_type)

    53   );

    54 }

    56 void __cpuidex(int cpu_info[4], int info_type, int info_index) {

    57   __asm__ volatile (

    58     "mov %%ebx, %%edi\n"

    59     "cpuid\n"

    60     "xchg %%edi, %%ebx\n"

    61     : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])

    62     : "a"(info_type), "c"(info_index)

    63   );

    64 }

    66 #else

    68 void __cpuid(int cpu_info[4], int info_type) {

    69   __asm__ volatile (

    70     "cpuid \n\t"

    71     : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])

    72     : "a"(info_type)

    73   );

    74 }

    76 void __cpuidex(int cpu_info[4], int info_type, int info_index) {

    77   __asm__ volatile (

    78     "cpuid \n\t"

    79     : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])

    80     : "a"(info_type), "c"(info_index)

    81   );

    82 }

    84 #endif

    85 #endif  // _MSC_VER

    86 #endif  // ARCH_CPU_X86_FAMILY

    88 void CPU::Initialize() {

    89 #if defined(ARCH_CPU_X86_FAMILY)

    90   int cpu_info[4] = {-1};

    91   char cpu_string[48];

    93   // __cpuid with an InfoType argument of 0 returns the number of

    94   // valid Ids in CPUInfo[0] and the CPU identification string in

    95   // the other three array elements. The CPU identification string is

    96   // not in linear order. The code below arranges the information

    97   // in a human readable form. The human readable order is CPUInfo[1] |

    98   // CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped

    99   // before using memcpy to copy these three array elements to cpu_string.

   100   __cpuid(cpu_info, 0);

   101   int num_ids = cpu_info[0];

   102   std::swap(cpu_info[2], cpu_info[3]);

   103   memcpy(cpu_string, &cpu_info[1], 3 * sizeof(cpu_info[1]));

   104   cpu_vendor_.assign(cpu_string, 3 * sizeof(cpu_info[1]));

   106   // Interpret CPU feature information.

   107   if (num_ids > 0) {

   108     __cpuid(cpu_info, 1);

   109     signature_ = cpu_info[0];

   110     stepping_ = cpu_info[0] & 0xf;

   111     model_ = ((cpu_info[0] >> 4) & 0xf) + ((cpu_info[0] >> 12) & 0xf0);

   112     family_ = (cpu_info[0] >> 8) & 0xf;

   113     type_ = (cpu_info[0] >> 12) & 0x3;

   114     ext_model_ = (cpu_info[0] >> 16) & 0xf;

   115     ext_family_ = (cpu_info[0] >> 20) & 0xff;

   116     has_mmx_ = (cpu_info[3] & 0x00800000) != 0;

   117     has_sse_ = (cpu_info[3] & 0x02000000) != 0;

   118     has_sse2_ = (cpu_info[3] & 0x04000000) != 0;

   119     has_sse3_ = (cpu_info[2] & 0x00000001) != 0;

   120     has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;

   121     has_sse41_ = (cpu_info[2] & 0x00080000) != 0;

   122     has_sse42_ = (cpu_info[2] & 0x00100000) != 0;

   123     has_avx_ = (cpu_info[2] & 0x10000000) != 0;

   124   }

   126   // Get the brand string of the cpu.

   127   __cpuid(cpu_info, 0x80000000);

   128   const int parameter_end = 0x80000004;

   129   int max_parameter = cpu_info[0];

   131   if (cpu_info[0] >= parameter_end) {

   132     char* cpu_string_ptr = cpu_string;

   134     for (int parameter = 0x80000002; parameter <= parameter_end &&

   135          cpu_string_ptr < &cpu_string[sizeof(cpu_string)]; parameter++) {

   136       __cpuid(cpu_info, parameter);

   137       memcpy(cpu_string_ptr, cpu_info, sizeof(cpu_info));

   138       cpu_string_ptr += sizeof(cpu_info);

   139     }

   140     cpu_brand_.assign(cpu_string, cpu_string_ptr - cpu_string);

   141   }

   143   const int parameter_containing_non_stop_time_stamp_counter = 0x80000007;

   144   if (max_parameter >= parameter_containing_non_stop_time_stamp_counter) {

   145     __cpuid(cpu_info, parameter_containing_non_stop_time_stamp_counter);

   146     has_non_stop_time_stamp_counter_ = (cpu_info[3] & (1 << 8)) != 0;

   147   }

   148 #endif

   149 }

   151 CPU::IntelMicroArchitecture CPU::GetIntelMicroArchitecture() const {

   152   if (has_avx()) return AVX;

   153   if (has_sse42()) return SSE42;

   154   if (has_sse41()) return SSE41;

   155   if (has_ssse3()) return SSSE3;

   156   if (has_sse3()) return SSE3;

   157   if (has_sse2()) return SSE2;

   158   if (has_sse()) return SSE;

   159   return PENTIUM;

   160 }

   162 }  // namespace base

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