michael@0: #include <stdlib.h>
michael@0: 
michael@0: #include "ia32_implicit.h"
michael@0: #include "ia32_insn.h"
michael@0: #include "ia32_reg.h"
michael@0: #include "x86_operand_list.h"
michael@0: 
michael@0: /* Conventions: Register operands which are aliases of another register 
michael@0:  *   operand (e.g. AX in one operand and AL in another) assume that the
michael@0:  *   operands are different registers and that alias tracking will resolve
michael@0:  *   data flow. This means that something like
michael@0:  *   	mov ax, al
michael@0:  *   would have 'write only' access for AX and 'read only' access for AL,
michael@0:  *   even though both AL and AX are read and written */
michael@0: typedef struct {
michael@0: 	uint32_t type;
michael@0: 	uint32_t operand;
michael@0: } op_implicit_list_t;
michael@0: 
michael@0: static op_implicit_list_t list_aaa[] = 
michael@0: 	/* 37 : AAA : rw AL */
michael@0: 	/* 3F : AAS : rw AL */
michael@0: 	{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}};	/* aaa */
michael@0: 
michael@0: static op_implicit_list_t list_aad[] = 
michael@0: 	/* D5 0A, D5 (ib) : AAD : rw AX */
michael@0: 	/* D4 0A, D4 (ib) : AAM : rw AX */
michael@0: 	{{ OP_R | OP_W, REG_WORD_OFFSET }, {0}};	/* aad */
michael@0: 
michael@0: static op_implicit_list_t list_call[] = 
michael@0: 	/* E8, FF, 9A, FF : CALL : rw ESP, rw EIP */
michael@0: 	/* C2, C3, CA, CB : RET  : rw ESP, rw EIP */
michael@0: 	{{ OP_R | OP_W, REG_EIP_INDEX }, 
michael@0: 	 { OP_R | OP_W, REG_ESP_INDEX }, {0}};	/* call, ret */
michael@0: 
michael@0: static op_implicit_list_t list_cbw[] = 
michael@0: 	/* 98 : CBW : r AL, rw AX */
michael@0: 	{{ OP_R | OP_W, REG_WORD_OFFSET },
michael@0: 	 { OP_R, REG_BYTE_OFFSET}, {0}};		/* cbw */
michael@0: 
michael@0: static op_implicit_list_t list_cwde[] = 
michael@0: 	/* 98 : CWDE : r AX, rw EAX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET },
michael@0: 	 { OP_R, REG_WORD_OFFSET }, {0}};		/* cwde */
michael@0: 
michael@0: static op_implicit_list_t list_clts[] = 
michael@0: 	/* 0F 06 : CLTS : rw CR0 */
michael@0: 	{{ OP_R | OP_W, REG_CTRL_OFFSET}, {0}};	/* clts */
michael@0: 
michael@0: static op_implicit_list_t list_cmpxchg[] = 
michael@0: 	/* 0F B0 : CMPXCHG : rw AL */
michael@0: 	{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}};	/* cmpxchg */
michael@0: 
michael@0: static op_implicit_list_t list_cmpxchgb[] = 
michael@0: 	/* 0F B1 : CMPXCHG : rw EAX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}};	/* cmpxchg */
michael@0: 
michael@0: static op_implicit_list_t list_cmpxchg8b[] = 
michael@0: 	/* 0F C7 : CMPXCHG8B : rw EDX, rw EAX, r ECX, r EBX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET }, 
michael@0: 	 { OP_R | OP_W, REG_DWORD_OFFSET + 2 }, 
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 1 }, 
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 3 }, {0}};	/* cmpxchg8b */
michael@0: 
michael@0: static op_implicit_list_t list_cpuid[] = 
michael@0: 	/* 0F A2 : CPUID : rw EAX, w EBX, w ECX, w EDX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET }, 
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 1 }, 
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 }, 
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 3 }, {0}};	/* cpuid */
michael@0: 
michael@0: static op_implicit_list_t list_cwd[] = 
michael@0: 	/* 99 : CWD/CWQ : rw EAX, w EDX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET }, 
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 }, {0}};	/* cwd */
michael@0: 
michael@0: static op_implicit_list_t list_daa[] = 
michael@0: 	/* 27 : DAA : rw AL */
michael@0: 	/* 2F : DAS : rw AL */
michael@0: 	{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}};	/* daa */
michael@0: 
michael@0: static op_implicit_list_t list_idiv[] = 
michael@0: 	/* F6 : DIV, IDIV : r AX, w AL, w AH */
michael@0: 	/* FIXED: first op was EAX, not Aw. TODO: verify! */
michael@0: 	{{ OP_R, REG_WORD_OFFSET }, 
michael@0: 	  { OP_W, REG_BYTE_OFFSET },
michael@0: 	  { OP_W, REG_BYTE_OFFSET + 4 }, {0}};	/* div */
michael@0: 
michael@0: static op_implicit_list_t list_div[] = 
michael@0: 	/* F7 : DIV, IDIV : rw EDX, rw EAX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET + 2 }, 
michael@0: 	  { OP_R | OP_W, REG_DWORD_OFFSET }, {0}};	/* div */
michael@0: 
michael@0: static op_implicit_list_t list_enter[] = 
michael@0: 	/* C8 : ENTER : rw ESP w EBP */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET + 4 }, 
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 5 }, {0}};	/* enter */
michael@0: 
michael@0: static op_implicit_list_t list_f2xm1[] = 
michael@0: 	/* D9 F0 : F2XM1 : rw ST(0) */
michael@0: 	/* D9 E1 : FABS : rw ST(0) */
michael@0: 	/* D9 E0 : FCHS : rw ST(0) */
michael@0: 	/* D9 FF : FCOS : rw ST(0)*/
michael@0: 	/* D8, DA : FDIV : rw ST(0) */
michael@0: 	/* D8, DA : FDIVR : rw ST(0) */
michael@0: 	/* D9 F2 : FPTAN : rw ST(0) */
michael@0: 	/* D9 FC : FRNDINT : rw ST(0) */
michael@0: 	/* D9 FB : FSINCOS : rw ST(0) */
michael@0: 	/* D9 FE : FSIN : rw ST(0) */
michael@0: 	/* D9 FA : FSQRT : rw ST(0) */
michael@0: 	/* D9 F4 : FXTRACT : rw ST(0) */
michael@0: 	{{ OP_R | OP_W, REG_FPU_OFFSET }, {0}};	/* f2xm1 */
michael@0: 
michael@0: static op_implicit_list_t list_fcom[] = 
michael@0: 	/* D8, DC, DE D9 : FCOM : r ST(0) */
michael@0: 	/* DE, DA : FICOM : r ST(0) */
michael@0: 	/* DF, D8 : FIST : r ST(0) */
michael@0: 	/* D9 E4 : FTST : r ST(0) */
michael@0: 	/* D9 E5 : FXAM : r ST(0) */
michael@0: 	{{ OP_R, REG_FPU_OFFSET }, {0}};		/* fcom */
michael@0: 
michael@0: static op_implicit_list_t list_fpatan[] = 
michael@0: 	/* D9 F3 : FPATAN : r ST(0), rw ST(1) */
michael@0: 	{{ OP_R, REG_FPU_OFFSET }, {0}};		/* fpatan */
michael@0: 
michael@0: static op_implicit_list_t list_fprem[] = 
michael@0: 	/* D9 F8, D9 F5 : FPREM : rw ST(0) r ST(1) */
michael@0: 	/* D9 FD : FSCALE : rw ST(0), r ST(1) */
michael@0: 	{{ OP_R | OP_W, REG_FPU_OFFSET }, 	
michael@0: 	 { OP_R, REG_FPU_OFFSET + 1 }, {0}};	/* fprem */
michael@0: 
michael@0: static op_implicit_list_t list_faddp[] = 
michael@0: 	/* DE C1 : FADDP : r ST(0), rw ST(1) */
michael@0: 	/* DE E9 : FSUBP : r ST(0), rw ST(1) */
michael@0: 	/* D9 F1 : FYL2X : r ST(0), rw ST(1) */
michael@0: 	/* D9 F9 : FYL2XP1 : r ST(0), rw ST(1) */
michael@0: 	{{ OP_R, REG_FPU_OFFSET },
michael@0: 	 { OP_R | OP_W, REG_FPU_OFFSET + 1 }, {0}};	/* faddp */
michael@0: 
michael@0: static op_implicit_list_t list_fucompp[] = 
michael@0: 	/* DA E9 : FUCOMPP : r ST(0), r ST(1) */
michael@0: 	{{ OP_R, REG_FPU_OFFSET },
michael@0: 	 { OP_R, REG_FPU_OFFSET + 1 }, {0}};	/* fucompp */
michael@0: 
michael@0: static op_implicit_list_t list_imul[] = 
michael@0: 	/* F6 : IMUL : r AL, w AX */
michael@0: 	/* F6 : MUL : r AL, w AX */
michael@0: 	{{ OP_R, REG_BYTE_OFFSET },
michael@0: 	 { OP_W, REG_WORD_OFFSET }, {0}};		/* imul */
michael@0: 
michael@0: static op_implicit_list_t list_mul[] = 
michael@0: 	/* F7 : IMUL : rw EAX, w EDX */
michael@0: 	/* F7 : MUL : rw EAX, w EDX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 }, {0}};	/* imul */
michael@0: 
michael@0: static op_implicit_list_t list_lahf[] = 
michael@0: 	/* 9F : LAHF : r EFLAGS, w AH */
michael@0: 	{{ OP_R, REG_FLAGS_INDEX },
michael@0: 	 { OP_W, REG_BYTE_OFFSET + 4 }, {0}};	/* lahf */
michael@0: 
michael@0: static op_implicit_list_t list_ldmxcsr[] = 
michael@0: 	/* 0F AE : LDMXCSR : w MXCSR SSE Control Status Reg */
michael@0: 	{{ OP_W, REG_MXCSG_INDEX }, {0}};		/* ldmxcsr */
michael@0: 
michael@0: static op_implicit_list_t list_leave[] = 
michael@0: 	/* C9 : LEAVE :  rw ESP, w EBP */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 5 }, {0}};	/* leave */
michael@0: 
michael@0: static op_implicit_list_t list_lgdt[] = 
michael@0: 	/* 0F 01 : LGDT : w GDTR */
michael@0: 	{{ OP_W, REG_GDTR_INDEX }, {0}};		/* lgdt */
michael@0: 
michael@0: static op_implicit_list_t list_lidt[] = 
michael@0: 	/* 0F 01 : LIDT : w IDTR */
michael@0: 	{{ OP_W, REG_IDTR_INDEX }, {0}};		/* lidt */
michael@0: 
michael@0: static op_implicit_list_t list_lldt[] = 
michael@0: 	/* 0F 00 : LLDT : w LDTR */
michael@0: 	{{ OP_W, REG_LDTR_INDEX }, {0}};		/* lldt */
michael@0: 
michael@0: static op_implicit_list_t list_lmsw[] = 
michael@0: 	/* 0F 01 : LMSW : w CR0 */
michael@0: 	{{ OP_W, REG_CTRL_OFFSET }, {0}};		/* lmsw */
michael@0: 
michael@0: static op_implicit_list_t list_loop[] = 
michael@0: 	/* E0, E1, E2 : LOOP : rw ECX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET + 1 }, {0}};/* loop */
michael@0: 
michael@0: static op_implicit_list_t list_ltr[] = 
michael@0: 	/* 0F 00 : LTR : w Task Register */
michael@0: 	{{ OP_W, REG_TR_INDEX }, {0}};		/* ltr */
michael@0: 
michael@0: static op_implicit_list_t list_pop[] = 
michael@0: 	/* 8F, 58, 1F, 07, 17, 0F A1, 0F A9 : POP : rw ESP */
michael@0: 	/* FF, 50, 6A, 68, 0E, 16, 1E, 06, 0F A0, 0F A8 : PUSH : rw ESP */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX }, {0}};	/* pop, push */
michael@0: 
michael@0: static op_implicit_list_t list_popad[] = 
michael@0: 	/* 61 : POPAD : rw esp, w edi esi ebp ebx edx ecx eax */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 7 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 6 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 5 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 3 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 1 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET }, {0}};		/* popad */
michael@0: 
michael@0: static op_implicit_list_t list_popfd[] = 
michael@0: 	/* 9D : POPFD : rw esp, w eflags */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX },
michael@0: 	 { OP_W, REG_FLAGS_INDEX }, {0}};		/* popfd */
michael@0: 
michael@0: static op_implicit_list_t list_pushad[] = 
michael@0: 	/* FF, 50, 6A, 68, 0E, 16, 1E, 06, 0F A0, 0F A8 : PUSH : rw ESP */
michael@0: 	/* 60 : PUSHAD : rw esp, r eax ecx edx ebx esp ebp esi edi */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX },
michael@0: 	 { OP_R, REG_DWORD_OFFSET },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 1 },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 2 },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 3 },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 5 },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 6 },
michael@0: 	 { OP_R, REG_DWORD_OFFSET + 7 }, {0}};	/* pushad */
michael@0: 
michael@0: static op_implicit_list_t list_pushfd[] = 
michael@0: 	/* 9C : PUSHFD : rw esp, r eflags */
michael@0: 	{{ OP_R | OP_W, REG_ESP_INDEX },
michael@0: 	 { OP_R, REG_FLAGS_INDEX }, {0}};		/* pushfd */
michael@0: 
michael@0: static op_implicit_list_t list_rdmsr[] = 
michael@0: 	/* 0F 32 : RDMSR : r ECX, w EDX, w EAX */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET + 1 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET }, {0}};	/* rdmsr */
michael@0: 
michael@0: static op_implicit_list_t list_rdpmc[] = 
michael@0: 	/* 0F 33 : RDPMC : r ECX, w EDX, w EAX */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET + 1 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET + 2 },
michael@0: 	 { OP_W, REG_DWORD_OFFSET }, {0}};		/* rdpmc */
michael@0: 
michael@0: static op_implicit_list_t list_rdtsc[] = 
michael@0: 	/* 0F 31 : RDTSC : rw EDX, rw EAX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET + 2 },
michael@0: 	 { OP_R | OP_W, REG_DWORD_OFFSET }, {0}};	/* rdtsc */
michael@0: 
michael@0: static op_implicit_list_t list_rep[] = 
michael@0: 	/* F3, F2 ... : REP : rw ECX */
michael@0: 	{{ OP_R | OP_W, REG_DWORD_OFFSET + 1 }, {0}};/* rep */
michael@0: 
michael@0: static op_implicit_list_t list_rsm[] = 
michael@0: 	/* 0F AA : RSM : r CR4, r CR0 */
michael@0: 	{{ OP_R, REG_CTRL_OFFSET + 4 }, 
michael@0: 	 { OP_R, REG_CTRL_OFFSET }, {0}};		/* rsm */
michael@0: 
michael@0: static op_implicit_list_t list_sahf[] = 
michael@0: 	/* 9E : SAHF : r ah, rw eflags (set SF ZF AF PF CF) */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sahf */
michael@0: 
michael@0: static op_implicit_list_t list_sgdt[] = 
michael@0: 	/* 0F : SGDT : r gdtr */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sgdt */
michael@0: 
michael@0: static op_implicit_list_t list_sidt[] = 
michael@0: 	/* 0F : SIDT : r idtr */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sidt */
michael@0: 
michael@0: static op_implicit_list_t list_sldt[] = 
michael@0: 	/* 0F : SLDT : r ldtr */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sldt */
michael@0: 
michael@0: static op_implicit_list_t list_smsw[] = 
michael@0: 	/* 0F : SMSW : r CR0 */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* smsw */
michael@0: 
michael@0: static op_implicit_list_t list_stmxcsr[] = 
michael@0: 	/* 0F AE : STMXCSR : r MXCSR */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* stmxcsr */
michael@0: 
michael@0: static op_implicit_list_t list_str[] = 
michael@0: 	/* 0F 00 : STR : r TR (task register) */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* str */
michael@0: 
michael@0: static op_implicit_list_t list_sysenter[] = 
michael@0: 	/* 0F 34 : SYSENTER : w cs, w eip, w ss, w esp, r CR0, w eflags
michael@0: 	 *         r sysenter_cs_msr, sysenter_esp_msr, sysenter_eip_msr */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sysenter */
michael@0: 
michael@0: static op_implicit_list_t list_sysexit[] = 
michael@0: 	/* 0F 35 : SYSEXIT : r edx, r ecx, w cs, w eip, w ss, w esp
michael@0: 	 * 	   r sysenter_cs_msr */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* sysexit */
michael@0: 
michael@0: static op_implicit_list_t list_wrmsr[] = 
michael@0: 	/* 0F 30 : WRMST : r edx, r eax, r ecx */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* wrmsr */
michael@0: 
michael@0: static op_implicit_list_t list_xlat[] = 
michael@0: 	/* D7 : XLAT : rw al r ebx (ptr) */
michael@0: 	/* TODO: finish this! */
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* xlat */
michael@0: /* TODO:
michael@0:  * monitor 0f 01 c8 eax OP_R ecx OP_R edx OP_R
michael@0:  * mwait 0f 01 c9 eax OP_R ecx OP_R
michael@0:  */
michael@0: static op_implicit_list_t list_monitor[] = 
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* monitor */
michael@0: static op_implicit_list_t list_mwait[] = 
michael@0: 	{{ OP_R, REG_DWORD_OFFSET }, {0}};		/* mwait */
michael@0: 
michael@0: op_implicit_list_t *op_implicit_list[] = {
michael@0: 	/* This is a list of implicit operands which are read/written by
michael@0: 	 * various x86 instructions. Note that modifications to the stack
michael@0: 	 * register are mentioned here, but that additional information on
michael@0: 	 * the effect an instruction has on the stack is contained in the
michael@0: 	 * x86_insn_t 'stack_mod' and 'stack_mod_val' fields. Use of the
michael@0: 	 * eflags register, i.e. setting, clearing, and testing flags, is
michael@0: 	 * not recorded here but rather in the flags_set and flags_tested
michael@0: 	 * fields of the x86_insn_t.*/
michael@0: 	NULL,
michael@0: 	list_aaa, list_aad, list_call, list_cbw,		/* 1 - 4 */
michael@0: 	list_cwde, list_clts, list_cmpxchg, list_cmpxchgb,	/* 5 - 8 */
michael@0: 	list_cmpxchg8b, list_cpuid, list_cwd, list_daa,		/* 9 - 12 */
michael@0: 	list_idiv, list_div, list_enter, list_f2xm1,		/* 13 - 16 */
michael@0: 	list_fcom, list_fpatan, list_fprem, list_faddp,		/* 17 - 20 */
michael@0: 	list_fucompp, list_imul, list_mul, list_lahf,		/* 21 - 24 */
michael@0: 	list_ldmxcsr, list_leave, list_lgdt, list_lidt,		/* 25 - 28 */
michael@0: 	list_lldt, list_lmsw, list_loop, list_ltr,		/* 29 - 32 */
michael@0: 	list_pop, list_popad, list_popfd, list_pushad,		/* 33 - 36 */
michael@0: 	list_pushfd, list_rdmsr, list_rdpmc, list_rdtsc,	/* 37 - 40 */
michael@0: 	/* NOTE: 'REP' is a hack since it is a prefix: if its position
michael@0: 	 * in the table changes, then change IDX_IMPLICIT_REP in the .h */
michael@0: 	list_rep, list_rsm, list_sahf, list_sgdt,		/* 41 - 44 */
michael@0: 	list_sidt, list_sldt, list_smsw, list_stmxcsr,		/* 45 - 48 */
michael@0: 	list_str, list_sysenter, list_sysexit, list_wrmsr,	/* 49 - 52 */
michael@0: 	list_xlat, list_monitor, list_mwait,			/* 53 - 55*/
michael@0: 	NULL						/* end of list */
michael@0:  };
michael@0: 
michael@0: #define LAST_IMPL_IDX 55
michael@0: 
michael@0: static void handle_impl_reg( x86_op_t *op, uint32_t val ) {
michael@0: 	x86_reg_t *reg = &op->data.reg;
michael@0: 	op->type = op_register;
michael@0: 	ia32_handle_register( reg, (unsigned int) val );
michael@0: 	switch (reg->size) {
michael@0: 		case 1:
michael@0: 			op->datatype = op_byte; break;
michael@0: 		case 2:
michael@0: 			op->datatype = op_word; break;
michael@0: 		case 4:
michael@0: 			op->datatype = op_dword; break;
michael@0: 		case 8:
michael@0: 			op->datatype = op_qword; break;
michael@0: 		case 10:
michael@0: 			op->datatype = op_extreal; break;
michael@0: 		case 16:
michael@0: 			op->datatype = op_dqword; break;
michael@0: 	}
michael@0: 	return;
michael@0: }
michael@0: 
michael@0: /* 'impl_idx' is the value from the opcode table: between 1 and LAST_IMPL_IDX */
michael@0: /* returns number of operands added */
michael@0: unsigned int ia32_insn_implicit_ops( x86_insn_t *insn, unsigned int impl_idx ) {
michael@0: 	op_implicit_list_t *list;
michael@0: 	x86_op_t *op;
michael@0: 	unsigned int num = 0;
michael@0: 
michael@0: 	if (! impl_idx || impl_idx > LAST_IMPL_IDX ) {
michael@0: 		return 0;
michael@0: 	}
michael@0: 
michael@0: 	for ( list = op_implicit_list[impl_idx]; list->type; list++, num++ ) {
michael@0: 		enum x86_op_access access = (enum x86_op_access) OP_PERM(list->type);
michael@0: 		enum x86_op_flags  flags  = (enum x86_op_flags) (OP_FLAGS(list->type) >> 12);
michael@0: 
michael@0: 		op = NULL;
michael@0: 		/* In some cases (MUL), EAX is an implicit operand hardcoded in
michael@0:                  * the instruction without being explicitly listed in assembly.
michael@0:                  * For this situation, find the hardcoded operand and add the
michael@0:                  * implied flag rather than adding a new implicit operand. */
michael@0: 		x86_oplist_t * existing;
michael@0: 		if (ia32_true_register_id(list->operand) == REG_DWORD_OFFSET) {
michael@0: 			for ( existing = insn->operands; existing; existing = existing->next ) {
michael@0: 				if (existing->op.type == op_register &&
michael@0: 	                            existing->op.data.reg.id == list->operand) {
michael@0: 					op = &existing->op;
michael@0: 					break;
michael@0: 				}
michael@0: 			}
michael@0: 		}
michael@0: 		if (!op) {
michael@0: 			op = x86_operand_new( insn );
michael@0: 			/* all implicit operands are registers */
michael@0: 			handle_impl_reg( op, list->operand );
michael@0: 			/* decrement the 'explicit count' incremented by default in
michael@0: 			 * x86_operand_new */
michael@0: 			insn->explicit_count = insn->explicit_count -1;
michael@0: 		}
michael@0: 		if (!op) {
michael@0: 			return num;	/* gah! return early */
michael@0: 		}
michael@0: 		op->access |= access;
michael@0: 		op->flags |= flags;
michael@0: 		op->flags |= op_implied;
michael@0: 	}
michael@0: 	
michael@0: 	return num;
michael@0: }