michael@0: /* michael@0: * Copyright © 2000 SuSE, Inc. michael@0: * Copyright © 2007 Red Hat, Inc. michael@0: * michael@0: * Permission to use, copy, modify, distribute, and sell this software and its michael@0: * documentation for any purpose is hereby granted without fee, provided that michael@0: * the above copyright notice appear in all copies and that both that michael@0: * copyright notice and this permission notice appear in supporting michael@0: * documentation, and that the name of SuSE not be used in advertising or michael@0: * publicity pertaining to distribution of the software without specific, michael@0: * written prior permission. SuSE makes no representations about the michael@0: * suitability of this software for any purpose. It is provided "as is" michael@0: * without express or implied warranty. michael@0: * michael@0: * SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL michael@0: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE michael@0: * BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES michael@0: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION michael@0: * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN michael@0: * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. michael@0: */ michael@0: #ifdef HAVE_CONFIG_H michael@0: #include michael@0: #endif michael@0: michael@0: #include "pixman-private.h" michael@0: michael@0: #if defined(USE_X86_MMX) || defined (USE_SSE2) michael@0: michael@0: /* The CPU detection code needs to be in a file not compiled with michael@0: * "-mmmx -msse", as gcc would generate CMOV instructions otherwise michael@0: * that would lead to SIGILL instructions on old CPUs that don't have michael@0: * it. michael@0: */ michael@0: michael@0: typedef enum michael@0: { michael@0: X86_MMX = (1 << 0), michael@0: X86_MMX_EXTENSIONS = (1 << 1), michael@0: X86_SSE = (1 << 2) | X86_MMX_EXTENSIONS, michael@0: X86_SSE2 = (1 << 3), michael@0: X86_CMOV = (1 << 4) michael@0: } cpu_features_t; michael@0: michael@0: #ifdef HAVE_GETISAX michael@0: michael@0: #include michael@0: michael@0: static cpu_features_t michael@0: detect_cpu_features (void) michael@0: { michael@0: cpu_features_t features = 0; michael@0: unsigned int result = 0; michael@0: michael@0: if (getisax (&result, 1)) michael@0: { michael@0: if (result & AV_386_CMOV) michael@0: features |= X86_CMOV; michael@0: if (result & AV_386_MMX) michael@0: features |= X86_MMX; michael@0: if (result & AV_386_AMD_MMX) michael@0: features |= X86_MMX_EXTENSIONS; michael@0: if (result & AV_386_SSE) michael@0: features |= X86_SSE; michael@0: if (result & AV_386_SSE2) michael@0: features |= X86_SSE2; michael@0: } michael@0: michael@0: return features; michael@0: } michael@0: michael@0: #else michael@0: michael@0: #define _PIXMAN_X86_64 \ michael@0: (defined(__amd64__) || defined(__x86_64__) || defined(_M_AMD64)) michael@0: michael@0: static pixman_bool_t michael@0: have_cpuid (void) michael@0: { michael@0: #if _PIXMAN_X86_64 || defined (_MSC_VER) michael@0: michael@0: return TRUE; michael@0: michael@0: #elif defined (__GNUC__) michael@0: uint32_t result; michael@0: michael@0: __asm__ volatile ( michael@0: "pushf" "\n\t" michael@0: "pop %%eax" "\n\t" michael@0: "mov %%eax, %%ecx" "\n\t" michael@0: "xor $0x00200000, %%eax" "\n\t" michael@0: "push %%eax" "\n\t" michael@0: "popf" "\n\t" michael@0: "pushf" "\n\t" michael@0: "pop %%eax" "\n\t" michael@0: "xor %%ecx, %%eax" "\n\t" michael@0: "mov %%eax, %0" "\n\t" michael@0: : "=r" (result) michael@0: : michael@0: : "%eax", "%ecx"); michael@0: michael@0: return !!result; michael@0: michael@0: #else michael@0: #error "Unknown compiler" michael@0: #endif michael@0: } michael@0: michael@0: static void michael@0: pixman_cpuid (uint32_t feature, michael@0: uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d) michael@0: { michael@0: #if defined (__GNUC__) michael@0: michael@0: #if _PIXMAN_X86_64 michael@0: __asm__ volatile ( michael@0: "cpuid" "\n\t" michael@0: : "=a" (*a), "=b" (*b), "=c" (*c), "=d" (*d) michael@0: : "a" (feature)); michael@0: #else michael@0: /* On x86-32 we need to be careful about the handling of %ebx michael@0: * and %esp. We can't declare either one as clobbered michael@0: * since they are special registers (%ebx is the "PIC michael@0: * register" holding an offset to global data, %esp the michael@0: * stack pointer), so we need to make sure that %ebx is michael@0: * preserved, and that %esp has its original value when michael@0: * accessing the output operands. michael@0: */ michael@0: __asm__ volatile ( michael@0: "xchg %%ebx, %1" "\n\t" michael@0: "cpuid" "\n\t" michael@0: "xchg %%ebx, %1" "\n\t" michael@0: : "=a" (*a), "=r" (*b), "=c" (*c), "=d" (*d) michael@0: : "a" (feature)); michael@0: #endif michael@0: michael@0: #elif defined (_MSC_VER) michael@0: int info[4]; michael@0: michael@0: __cpuid (info, feature); michael@0: michael@0: *a = info[0]; michael@0: *b = info[1]; michael@0: *c = info[2]; michael@0: *d = info[3]; michael@0: #else michael@0: #error Unknown compiler michael@0: #endif michael@0: } michael@0: michael@0: static cpu_features_t michael@0: detect_cpu_features (void) michael@0: { michael@0: uint32_t a, b, c, d; michael@0: cpu_features_t features = 0; michael@0: michael@0: if (!have_cpuid()) michael@0: return features; michael@0: michael@0: /* Get feature bits */ michael@0: pixman_cpuid (0x01, &a, &b, &c, &d); michael@0: if (d & (1 << 15)) michael@0: features |= X86_CMOV; michael@0: if (d & (1 << 23)) michael@0: features |= X86_MMX; michael@0: if (d & (1 << 25)) michael@0: features |= X86_SSE; michael@0: if (d & (1 << 26)) michael@0: features |= X86_SSE2; michael@0: michael@0: /* Check for AMD specific features */ michael@0: if ((features & X86_MMX) && !(features & X86_SSE)) michael@0: { michael@0: char vendor[13]; michael@0: michael@0: /* Get vendor string */ michael@0: memset (vendor, 0, sizeof vendor); michael@0: michael@0: pixman_cpuid (0x00, &a, &b, &c, &d); michael@0: memcpy (vendor + 0, &b, 4); michael@0: memcpy (vendor + 4, &d, 4); michael@0: memcpy (vendor + 8, &c, 4); michael@0: michael@0: if (strcmp (vendor, "AuthenticAMD") == 0 || michael@0: strcmp (vendor, "Geode by NSC") == 0) michael@0: { michael@0: pixman_cpuid (0x80000000, &a, &b, &c, &d); michael@0: if (a >= 0x80000001) michael@0: { michael@0: pixman_cpuid (0x80000001, &a, &b, &c, &d); michael@0: michael@0: if (d & (1 << 22)) michael@0: features |= X86_MMX_EXTENSIONS; michael@0: } michael@0: } michael@0: } michael@0: michael@0: return features; michael@0: } michael@0: michael@0: #endif michael@0: michael@0: static pixman_bool_t michael@0: have_feature (cpu_features_t feature) michael@0: { michael@0: static pixman_bool_t initialized; michael@0: static cpu_features_t features; michael@0: michael@0: if (!initialized) michael@0: { michael@0: features = detect_cpu_features(); michael@0: initialized = TRUE; michael@0: } michael@0: michael@0: return (features & feature) == feature; michael@0: } michael@0: michael@0: #endif michael@0: michael@0: pixman_implementation_t * michael@0: _pixman_x86_get_implementations (pixman_implementation_t *imp) michael@0: { michael@0: #define MMX_BITS (X86_MMX | X86_MMX_EXTENSIONS) michael@0: #define SSE2_BITS (X86_MMX | X86_MMX_EXTENSIONS | X86_SSE | X86_SSE2) michael@0: michael@0: #ifdef USE_X86_MMX michael@0: if (!_pixman_disabled ("mmx") && have_feature (MMX_BITS)) michael@0: imp = _pixman_implementation_create_mmx (imp); michael@0: #endif michael@0: michael@0: #ifdef USE_SSE2 michael@0: if (!_pixman_disabled ("sse2") && have_feature (SSE2_BITS)) michael@0: imp = _pixman_implementation_create_sse2 (imp); michael@0: #endif michael@0: michael@0: return imp; michael@0: }