michael@0: // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
michael@0: // Use of this source code is governed by a BSD-style license that can be
michael@0: // found in the LICENSE file.
michael@0: 
michael@0: // This module gets enough CPU information to optimize the
michael@0: // atomicops module on x86.
michael@0: 
michael@0: #include <string.h>
michael@0: 
michael@0: #include "base/atomicops.h"
michael@0: #include "base/basictypes.h"
michael@0: 
michael@0: // This file only makes sense with atomicops_internals_x86_gcc.h -- it
michael@0: // depends on structs that are defined in that file.  If atomicops.h
michael@0: // doesn't sub-include that file, then we aren't needed, and shouldn't
michael@0: // try to do anything.
michael@0: #ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
michael@0: 
michael@0: // Inline cpuid instruction.  In PIC compilations, %ebx contains the address
michael@0: // of the global offset table.  To avoid breaking such executables, this code
michael@0: // must preserve that register's value across cpuid instructions.
michael@0: #if defined(__i386__)
michael@0: #define cpuid(a, b, c, d, inp) \
michael@0:   asm ("mov %%ebx, %%edi\n"    \
michael@0:        "cpuid\n"               \
michael@0:        "xchg %%edi, %%ebx\n"   \
michael@0:        : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
michael@0: #elif defined (__x86_64__)
michael@0: #define cpuid(a, b, c, d, inp) \
michael@0:   asm ("mov %%rbx, %%rdi\n"    \
michael@0:        "cpuid\n"               \
michael@0:        "xchg %%rdi, %%rbx\n"   \
michael@0:        : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
michael@0: #endif
michael@0: 
michael@0: #if defined(cpuid)        // initialize the struct only on x86
michael@0: 
michael@0: // Set the flags so that code will run correctly and conservatively, so even
michael@0: // if we haven't been initialized yet, we're probably single threaded, and our
michael@0: // default values should hopefully be pretty safe.
michael@0: struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
michael@0:   false,          // bug can't exist before process spawns multiple threads
michael@0:   false,          // no SSE2
michael@0: };
michael@0: 
michael@0: // Initialize the AtomicOps_Internalx86CPUFeatures struct.
michael@0: static void AtomicOps_Internalx86CPUFeaturesInit() {
michael@0:   uint32_t eax;
michael@0:   uint32_t ebx;
michael@0:   uint32_t ecx;
michael@0:   uint32_t edx;
michael@0: 
michael@0:   // Get vendor string (issue CPUID with eax = 0)
michael@0:   cpuid(eax, ebx, ecx, edx, 0);
michael@0:   char vendor[13];
michael@0:   memcpy(vendor, &ebx, 4);
michael@0:   memcpy(vendor + 4, &edx, 4);
michael@0:   memcpy(vendor + 8, &ecx, 4);
michael@0:   vendor[12] = 0;
michael@0: 
michael@0:   // get feature flags in ecx/edx, and family/model in eax
michael@0:   cpuid(eax, ebx, ecx, edx, 1);
michael@0: 
michael@0:   int family = (eax >> 8) & 0xf;        // family and model fields
michael@0:   int model = (eax >> 4) & 0xf;
michael@0:   if (family == 0xf) {                  // use extended family and model fields
michael@0:     family += (eax >> 20) & 0xff;
michael@0:     model += ((eax >> 16) & 0xf) << 4;
michael@0:   }
michael@0: 
michael@0:   // Opteron Rev E has a bug in which on very rare occasions a locked
michael@0:   // instruction doesn't act as a read-acquire barrier if followed by a
michael@0:   // non-locked read-modify-write instruction.  Rev F has this bug in
michael@0:   // pre-release versions, but not in versions released to customers,
michael@0:   // so we test only for Rev E, which is family 15, model 32..63 inclusive.
michael@0:   if (strcmp(vendor, "AuthenticAMD") == 0 &&       // AMD
michael@0:       family == 15 &&
michael@0:       32 <= model && model <= 63) {
michael@0:     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
michael@0:   } else {
michael@0:     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
michael@0:   }
michael@0: 
michael@0:   // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
michael@0:   AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
michael@0: }
michael@0: 
michael@0: namespace {
michael@0: 
michael@0: class AtomicOpsx86Initializer {
michael@0:  public:
michael@0:   AtomicOpsx86Initializer() {
michael@0:     AtomicOps_Internalx86CPUFeaturesInit();
michael@0:   }
michael@0: };
michael@0: 
michael@0: // A global to get use initialized on startup via static initialization :/
michael@0: AtomicOpsx86Initializer g_initer;
michael@0: 
michael@0: }  // namespace
michael@0: 
michael@0: #endif  // if x86
michael@0: 
michael@0: #endif  // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_