michael@0: /* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*- michael@0: * vim: set ts=8 sts=4 et sw=4 tw=99: michael@0: * This Source Code Form is subject to the terms of the Mozilla Public michael@0: * License, v. 2.0. If a copy of the MPL was not distributed with this michael@0: * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ michael@0: michael@0: #ifndef jit_arm_MacroAssembler_arm_h michael@0: #define jit_arm_MacroAssembler_arm_h michael@0: michael@0: #include "mozilla/DebugOnly.h" michael@0: michael@0: #include "jsopcode.h" michael@0: michael@0: #include "jit/arm/Assembler-arm.h" michael@0: #include "jit/IonCaches.h" michael@0: #include "jit/IonFrames.h" michael@0: #include "jit/MoveResolver.h" michael@0: michael@0: using mozilla::DebugOnly; michael@0: michael@0: namespace js { michael@0: namespace jit { michael@0: michael@0: static Register CallReg = ip; michael@0: static const int defaultShift = 3; michael@0: JS_STATIC_ASSERT(1 << defaultShift == sizeof(jsval)); michael@0: michael@0: // MacroAssemblerARM is inheriting form Assembler defined in Assembler-arm.{h,cpp} michael@0: class MacroAssemblerARM : public Assembler michael@0: { michael@0: protected: michael@0: // On ARM, some instructions require a second scratch register. This register michael@0: // defaults to lr, since it's non-allocatable (as it can be clobbered by some michael@0: // instructions). Allow the baseline compiler to override this though, since michael@0: // baseline IC stubs rely on lr holding the return address. michael@0: Register secondScratchReg_; michael@0: michael@0: // higher level tag testing code michael@0: Operand ToPayload(Operand base) { michael@0: return Operand(Register::FromCode(base.base()), base.disp()); michael@0: } michael@0: Address ToPayload(Address base) { michael@0: return ToPayload(Operand(base)).toAddress(); michael@0: } michael@0: Operand ToType(Operand base) { michael@0: return Operand(Register::FromCode(base.base()), base.disp() + sizeof(void *)); michael@0: } michael@0: Address ToType(Address base) { michael@0: return ToType(Operand(base)).toAddress(); michael@0: } michael@0: michael@0: public: michael@0: MacroAssemblerARM() michael@0: : secondScratchReg_(lr) michael@0: { } michael@0: michael@0: void setSecondScratchReg(Register reg) { michael@0: JS_ASSERT(reg != ScratchRegister); michael@0: secondScratchReg_ = reg; michael@0: } michael@0: michael@0: void convertBoolToInt32(Register source, Register dest); michael@0: void convertInt32ToDouble(const Register &src, const FloatRegister &dest); michael@0: void convertInt32ToDouble(const Address &src, FloatRegister dest); michael@0: void convertUInt32ToFloat32(const Register &src, const FloatRegister &dest); michael@0: void convertUInt32ToDouble(const Register &src, const FloatRegister &dest); michael@0: void convertDoubleToFloat32(const FloatRegister &src, const FloatRegister &dest, michael@0: Condition c = Always); michael@0: void branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail); michael@0: void convertDoubleToInt32(const FloatRegister &src, const Register &dest, Label *fail, michael@0: bool negativeZeroCheck = true); michael@0: void convertFloat32ToInt32(const FloatRegister &src, const Register &dest, Label *fail, michael@0: bool negativeZeroCheck = true); michael@0: michael@0: void convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest); michael@0: void branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail); michael@0: void convertInt32ToFloat32(const Register &src, const FloatRegister &dest); michael@0: void convertInt32ToFloat32(const Address &src, FloatRegister dest); michael@0: michael@0: void addDouble(FloatRegister src, FloatRegister dest); michael@0: void subDouble(FloatRegister src, FloatRegister dest); michael@0: void mulDouble(FloatRegister src, FloatRegister dest); michael@0: void divDouble(FloatRegister src, FloatRegister dest); michael@0: michael@0: void negateDouble(FloatRegister reg); michael@0: void inc64(AbsoluteAddress dest); michael@0: michael@0: // somewhat direct wrappers for the low-level assembler funcitons michael@0: // bitops michael@0: // attempt to encode a virtual alu instruction using michael@0: // two real instructions. michael@0: private: michael@0: bool alu_dbl(Register src1, Imm32 imm, Register dest, ALUOp op, michael@0: SetCond_ sc, Condition c); michael@0: michael@0: public: michael@0: void ma_alu(Register src1, Operand2 op2, Register dest, ALUOp op, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_alu(Register src1, Imm32 imm, Register dest, michael@0: ALUOp op, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_alu(Register src1, Operand op2, Register dest, ALUOp op, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_nop(); michael@0: void ma_movPatchable(Imm32 imm, Register dest, Assembler::Condition c, michael@0: RelocStyle rs, Instruction *i = nullptr); michael@0: void ma_movPatchable(ImmPtr imm, Register dest, Assembler::Condition c, michael@0: RelocStyle rs, Instruction *i = nullptr); michael@0: // These should likely be wrapped up as a set of macros michael@0: // or something like that. I cannot think of a good reason michael@0: // to explicitly have all of this code. michael@0: // ALU based ops michael@0: // mov michael@0: void ma_mov(Register src, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_mov(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_mov(ImmWord imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_mov(const ImmGCPtr &ptr, Register dest); michael@0: michael@0: // Shifts (just a move with a shifting op2) michael@0: void ma_lsl(Imm32 shift, Register src, Register dst); michael@0: void ma_lsr(Imm32 shift, Register src, Register dst); michael@0: void ma_asr(Imm32 shift, Register src, Register dst); michael@0: void ma_ror(Imm32 shift, Register src, Register dst); michael@0: void ma_rol(Imm32 shift, Register src, Register dst); michael@0: // Shifts (just a move with a shifting op2) michael@0: void ma_lsl(Register shift, Register src, Register dst); michael@0: void ma_lsr(Register shift, Register src, Register dst); michael@0: void ma_asr(Register shift, Register src, Register dst); michael@0: void ma_ror(Register shift, Register src, Register dst); michael@0: void ma_rol(Register shift, Register src, Register dst); michael@0: michael@0: // Move not (dest <- ~src) michael@0: void ma_mvn(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: michael@0: void ma_mvn(Register src1, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // Negate (dest <- -src) implemented as rsb dest, src, 0 michael@0: void ma_neg(Register src, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // and michael@0: void ma_and(Register src, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_and(Register src1, Register src2, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_and(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_and(Imm32 imm, Register src1, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: michael@0: michael@0: // bit clear (dest <- dest & ~imm) or (dest <- src1 & ~src2) michael@0: void ma_bic(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // exclusive or michael@0: void ma_eor(Register src, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_eor(Register src1, Register src2, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_eor(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_eor(Imm32 imm, Register src1, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: michael@0: // or michael@0: void ma_orr(Register src, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_orr(Register src1, Register src2, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_orr(Imm32 imm, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: void ma_orr(Imm32 imm, Register src1, Register dest, michael@0: SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: michael@0: // arithmetic based ops michael@0: // add with carry michael@0: void ma_adc(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_adc(Register src, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_adc(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // add michael@0: void ma_add(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_add(Register src1, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_add(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_add(Register src1, Operand op, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_add(Register src1, Imm32 op, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // subtract with carry michael@0: void ma_sbc(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sbc(Register src1, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sbc(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // subtract michael@0: void ma_sub(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sub(Register src1, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sub(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sub(Register src1, Operand op, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_sub(Register src1, Imm32 op, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // reverse subtract michael@0: void ma_rsb(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_rsb(Register src1, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_rsb(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_rsb(Register src1, Imm32 op2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // reverse subtract with carry michael@0: void ma_rsc(Imm32 imm, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_rsc(Register src1, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: void ma_rsc(Register src1, Register src2, Register dest, SetCond_ sc = NoSetCond, Condition c = Always); michael@0: michael@0: // compares/tests michael@0: // compare negative (sets condition codes as src1 + src2 would) michael@0: void ma_cmn(Register src1, Imm32 imm, Condition c = Always); michael@0: void ma_cmn(Register src1, Register src2, Condition c = Always); michael@0: void ma_cmn(Register src1, Operand op, Condition c = Always); michael@0: michael@0: // compare (src - src2) michael@0: void ma_cmp(Register src1, Imm32 imm, Condition c = Always); michael@0: void ma_cmp(Register src1, ImmWord ptr, Condition c = Always); michael@0: void ma_cmp(Register src1, ImmGCPtr ptr, Condition c = Always); michael@0: void ma_cmp(Register src1, Operand op, Condition c = Always); michael@0: void ma_cmp(Register src1, Register src2, Condition c = Always); michael@0: michael@0: michael@0: // test for equality, (src1^src2) michael@0: void ma_teq(Register src1, Imm32 imm, Condition c = Always); michael@0: void ma_teq(Register src1, Register src2, Condition c = Always); michael@0: void ma_teq(Register src1, Operand op, Condition c = Always); michael@0: michael@0: michael@0: // test (src1 & src2) michael@0: void ma_tst(Register src1, Imm32 imm, Condition c = Always); michael@0: void ma_tst(Register src1, Register src2, Condition c = Always); michael@0: void ma_tst(Register src1, Operand op, Condition c = Always); michael@0: michael@0: // multiplies. For now, there are only two that we care about. michael@0: void ma_mul(Register src1, Register src2, Register dest); michael@0: void ma_mul(Register src1, Imm32 imm, Register dest); michael@0: Condition ma_check_mul(Register src1, Register src2, Register dest, Condition cond); michael@0: Condition ma_check_mul(Register src1, Imm32 imm, Register dest, Condition cond); michael@0: michael@0: // fast mod, uses scratch registers, and thus needs to be in the assembler michael@0: // implicitly assumes that we can overwrite dest at the beginning of the sequence michael@0: void ma_mod_mask(Register src, Register dest, Register hold, Register tmp, michael@0: int32_t shift); michael@0: michael@0: // mod, depends on integer divide instructions being supported michael@0: void ma_smod(Register num, Register div, Register dest); michael@0: void ma_umod(Register num, Register div, Register dest); michael@0: michael@0: // division, depends on integer divide instructions being supported michael@0: void ma_sdiv(Register num, Register div, Register dest, Condition cond = Always); michael@0: void ma_udiv(Register num, Register div, Register dest, Condition cond = Always); michael@0: michael@0: // memory michael@0: // shortcut for when we know we're transferring 32 bits of data michael@0: void ma_dtr(LoadStore ls, Register rn, Imm32 offset, Register rt, michael@0: Index mode = Offset, Condition cc = Always); michael@0: michael@0: void ma_dtr(LoadStore ls, Register rn, Register rm, Register rt, michael@0: Index mode = Offset, Condition cc = Always); michael@0: michael@0: michael@0: void ma_str(Register rt, DTRAddr addr, Index mode = Offset, Condition cc = Always); michael@0: void ma_str(Register rt, const Operand &addr, Index mode = Offset, Condition cc = Always); michael@0: void ma_dtr(LoadStore ls, Register rt, const Operand &addr, Index mode, Condition cc); michael@0: michael@0: void ma_ldr(DTRAddr addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: void ma_ldr(const Operand &addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: michael@0: void ma_ldrb(DTRAddr addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: void ma_ldrh(EDtrAddr addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: void ma_ldrsh(EDtrAddr addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: void ma_ldrsb(EDtrAddr addr, Register rt, Index mode = Offset, Condition cc = Always); michael@0: void ma_ldrd(EDtrAddr addr, Register rt, DebugOnly rt2, Index mode = Offset, Condition cc = Always); michael@0: void ma_strb(Register rt, DTRAddr addr, Index mode = Offset, Condition cc = Always); michael@0: void ma_strh(Register rt, EDtrAddr addr, Index mode = Offset, Condition cc = Always); michael@0: void ma_strd(Register rt, DebugOnly rt2, EDtrAddr addr, Index mode = Offset, Condition cc = Always); michael@0: // specialty for moving N bits of data, where n == 8,16,32,64 michael@0: BufferOffset ma_dataTransferN(LoadStore ls, int size, bool IsSigned, michael@0: Register rn, Register rm, Register rt, michael@0: Index mode = Offset, Condition cc = Always, unsigned scale = TimesOne); michael@0: michael@0: BufferOffset ma_dataTransferN(LoadStore ls, int size, bool IsSigned, michael@0: Register rn, Imm32 offset, Register rt, michael@0: Index mode = Offset, Condition cc = Always); michael@0: void ma_pop(Register r); michael@0: void ma_push(Register r); michael@0: michael@0: void ma_vpop(VFPRegister r); michael@0: void ma_vpush(VFPRegister r); michael@0: michael@0: // branches when done from within arm-specific code michael@0: BufferOffset ma_b(Label *dest, Condition c = Always, bool isPatchable = false); michael@0: void ma_bx(Register dest, Condition c = Always); michael@0: michael@0: void ma_b(void *target, Relocation::Kind reloc, Condition c = Always); michael@0: michael@0: // this is almost NEVER necessary, we'll basically never be calling a label michael@0: // except, possibly in the crazy bailout-table case. michael@0: void ma_bl(Label *dest, Condition c = Always); michael@0: michael@0: void ma_blx(Register dest, Condition c = Always); michael@0: michael@0: //VFP/ALU michael@0: void ma_vadd(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: void ma_vsub(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: michael@0: void ma_vmul(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: void ma_vdiv(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: michael@0: void ma_vneg(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vmov(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vmov_f32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vabs(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vabs_f32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: void ma_vsqrt(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vsqrt_f32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: void ma_vimm(double value, FloatRegister dest, Condition cc = Always); michael@0: void ma_vimm_f32(float value, FloatRegister dest, Condition cc = Always); michael@0: michael@0: void ma_vcmp(FloatRegister src1, FloatRegister src2, Condition cc = Always); michael@0: void ma_vcmp_f32(FloatRegister src1, FloatRegister src2, Condition cc = Always); michael@0: void ma_vcmpz(FloatRegister src1, Condition cc = Always); michael@0: void ma_vcmpz_f32(FloatRegister src1, Condition cc = Always); michael@0: michael@0: void ma_vadd_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: void ma_vsub_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: michael@0: void ma_vmul_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: void ma_vdiv_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst); michael@0: michael@0: void ma_vneg_f32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: // source is F64, dest is I32 michael@0: void ma_vcvt_F64_I32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vcvt_F64_U32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: // source is I32, dest is F64 michael@0: void ma_vcvt_I32_F64(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vcvt_U32_F64(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: // source is F32, dest is I32 michael@0: void ma_vcvt_F32_I32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vcvt_F32_U32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: // source is I32, dest is F32 michael@0: void ma_vcvt_I32_F32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: void ma_vcvt_U32_F32(FloatRegister src, FloatRegister dest, Condition cc = Always); michael@0: michael@0: void ma_vxfer(FloatRegister src, Register dest, Condition cc = Always); michael@0: void ma_vxfer(FloatRegister src, Register dest1, Register dest2, Condition cc = Always); michael@0: michael@0: void ma_vxfer(VFPRegister src, Register dest, Condition cc = Always); michael@0: void ma_vxfer(VFPRegister src, Register dest1, Register dest2, Condition cc = Always); michael@0: michael@0: void ma_vxfer(Register src1, Register src2, FloatRegister dest, Condition cc = Always); michael@0: michael@0: BufferOffset ma_vdtr(LoadStore ls, const Operand &addr, VFPRegister dest, Condition cc = Always); michael@0: michael@0: michael@0: BufferOffset ma_vldr(VFPAddr addr, VFPRegister dest, Condition cc = Always); michael@0: BufferOffset ma_vldr(const Operand &addr, VFPRegister dest, Condition cc = Always); michael@0: BufferOffset ma_vldr(VFPRegister src, Register base, Register index, int32_t shift = defaultShift, Condition cc = Always); michael@0: michael@0: BufferOffset ma_vstr(VFPRegister src, VFPAddr addr, Condition cc = Always); michael@0: BufferOffset ma_vstr(VFPRegister src, const Operand &addr, Condition cc = Always); michael@0: michael@0: BufferOffset ma_vstr(VFPRegister src, Register base, Register index, int32_t shift = defaultShift, Condition cc = Always); michael@0: // calls an Ion function, assumes that the stack is untouched (8 byte alinged) michael@0: void ma_callIon(const Register reg); michael@0: // callso an Ion function, assuming that sp has already been decremented michael@0: void ma_callIonNoPush(const Register reg); michael@0: // calls an ion function, assuming that the stack is currently not 8 byte aligned michael@0: void ma_callIonHalfPush(const Register reg); michael@0: michael@0: void ma_call(ImmPtr dest); michael@0: michael@0: // calls reg, storing the return address into sp[0] michael@0: void ma_callAndStoreRet(const Register reg, uint32_t stackArgBytes); michael@0: michael@0: // Float registers can only be loaded/stored in continuous runs michael@0: // when using vstm/vldm. michael@0: // This function breaks set into continuous runs and loads/stores michael@0: // them at [rm]. rm will be modified and left in a state logically michael@0: // suitable for the next load/store. michael@0: // Returns the offset from [dm] for the logical next load/store. michael@0: int32_t transferMultipleByRuns(FloatRegisterSet set, LoadStore ls, michael@0: Register rm, DTMMode mode) michael@0: { michael@0: if (mode == IA) { michael@0: return transferMultipleByRunsImpl michael@0: (set, ls, rm, mode, 1); michael@0: } michael@0: if (mode == DB) { michael@0: return transferMultipleByRunsImpl michael@0: (set, ls, rm, mode, -1); michael@0: } michael@0: MOZ_ASSUME_UNREACHABLE("Invalid data transfer addressing mode"); michael@0: } michael@0: michael@0: private: michael@0: // Implementation for transferMultipleByRuns so we can use different michael@0: // iterators for forward/backward traversals. michael@0: // The sign argument should be 1 if we traverse forwards, -1 if we michael@0: // traverse backwards. michael@0: template int32_t michael@0: transferMultipleByRunsImpl(FloatRegisterSet set, LoadStore ls, michael@0: Register rm, DTMMode mode, int32_t sign) michael@0: { michael@0: JS_ASSERT(sign == 1 || sign == -1); michael@0: michael@0: int32_t delta = sign * sizeof(double); michael@0: int32_t offset = 0; michael@0: RegisterIterator iter(set); michael@0: while (iter.more()) { michael@0: startFloatTransferM(ls, rm, mode, WriteBack); michael@0: int32_t reg = (*iter).code_; michael@0: do { michael@0: offset += delta; michael@0: transferFloatReg(*iter); michael@0: } while ((++iter).more() && (*iter).code_ == (reg += sign)); michael@0: finishFloatTransfer(); michael@0: } michael@0: michael@0: JS_ASSERT(offset == static_cast(set.size() * sizeof(double)) * sign); michael@0: return offset; michael@0: } michael@0: }; michael@0: michael@0: class MacroAssemblerARMCompat : public MacroAssemblerARM michael@0: { michael@0: // Number of bytes the stack is adjusted inside a call to C. Calls to C may michael@0: // not be nested. michael@0: bool inCall_; michael@0: uint32_t args_; michael@0: // The actual number of arguments that were passed, used to assert that michael@0: // the initial number of arguments declared was correct. michael@0: uint32_t passedArgs_; michael@0: uint32_t passedArgTypes_; michael@0: michael@0: // ARM treats arguments as a vector in registers/memory, that looks like: michael@0: // { r0, r1, r2, r3, [sp], [sp,+4], [sp,+8] ... } michael@0: // usedIntSlots_ keeps track of how many of these have been used. michael@0: // It bears a passing resemblance to passedArgs_, but a single argument michael@0: // can effectively use between one and three slots depending on its size and michael@0: // alignment requirements michael@0: uint32_t usedIntSlots_; michael@0: #if defined(JS_CODEGEN_ARM_HARDFP) || defined(JS_ARM_SIMULATOR) michael@0: uint32_t usedFloatSlots_; michael@0: bool usedFloat32_; michael@0: uint32_t padding_; michael@0: #endif michael@0: bool dynamicAlignment_; michael@0: michael@0: bool enoughMemory_; michael@0: michael@0: // Used to work around the move resolver's lack of support for michael@0: // moving into register pairs, which the softfp ABI needs. michael@0: mozilla::Array floatArgsInGPR; michael@0: mozilla::Array floatArgsInGPRValid; michael@0: michael@0: // Compute space needed for the function call and set the properties of the michael@0: // callee. It returns the space which has to be allocated for calling the michael@0: // function. michael@0: // michael@0: // arg Number of arguments of the function. michael@0: void setupABICall(uint32_t arg); michael@0: michael@0: protected: michael@0: MoveResolver moveResolver_; michael@0: michael@0: // Extra bytes currently pushed onto the frame beyond frameDepth_. This is michael@0: // needed to compute offsets to stack slots while temporary space has been michael@0: // reserved for unexpected spills or C++ function calls. It is maintained michael@0: // by functions which track stack alignment, which for clear distinction michael@0: // use StudlyCaps (for example, Push, Pop). michael@0: uint32_t framePushed_; michael@0: void adjustFrame(int value) { michael@0: setFramePushed(framePushed_ + value); michael@0: } michael@0: public: michael@0: MacroAssemblerARMCompat() michael@0: : inCall_(false), michael@0: enoughMemory_(true), michael@0: framePushed_(0) michael@0: { } michael@0: bool oom() const { michael@0: return Assembler::oom() || !enoughMemory_; michael@0: } michael@0: michael@0: public: michael@0: using MacroAssemblerARM::call; michael@0: michael@0: // jumps + other functions that should be called from michael@0: // non-arm specific code... michael@0: // basically, an x86 front end on top of the ARM code. michael@0: void j(Condition code , Label *dest) michael@0: { michael@0: as_b(dest, code); michael@0: } michael@0: void j(Label *dest) michael@0: { michael@0: as_b(dest, Always); michael@0: } michael@0: michael@0: void mov(Register src, Register dest) { michael@0: ma_mov(src, dest); michael@0: } michael@0: void mov(ImmWord imm, Register dest) { michael@0: ma_mov(Imm32(imm.value), dest); michael@0: } michael@0: void mov(ImmPtr imm, Register dest) { michael@0: mov(ImmWord(uintptr_t(imm.value)), dest); michael@0: } michael@0: void mov(Register src, Address dest) { michael@0: MOZ_ASSUME_UNREACHABLE("NYI-IC"); michael@0: } michael@0: void mov(Address src, Register dest) { michael@0: MOZ_ASSUME_UNREACHABLE("NYI-IC"); michael@0: } michael@0: michael@0: void call(const Register reg) { michael@0: as_blx(reg); michael@0: } michael@0: void call(Label *label) { michael@0: // for now, assume that it'll be nearby? michael@0: as_bl(label, Always); michael@0: } michael@0: void call(ImmWord imm) { michael@0: call(ImmPtr((void*)imm.value)); michael@0: } michael@0: void call(ImmPtr imm) { michael@0: BufferOffset bo = m_buffer.nextOffset(); michael@0: addPendingJump(bo, imm, Relocation::HARDCODED); michael@0: ma_call(imm); michael@0: } michael@0: void call(AsmJSImmPtr imm) { michael@0: movePtr(imm, CallReg); michael@0: call(CallReg); michael@0: } michael@0: void call(JitCode *c) { michael@0: BufferOffset bo = m_buffer.nextOffset(); michael@0: addPendingJump(bo, ImmPtr(c->raw()), Relocation::JITCODE); michael@0: RelocStyle rs; michael@0: if (hasMOVWT()) michael@0: rs = L_MOVWT; michael@0: else michael@0: rs = L_LDR; michael@0: michael@0: ma_movPatchable(ImmPtr(c->raw()), ScratchRegister, Always, rs); michael@0: ma_callIonHalfPush(ScratchRegister); michael@0: } michael@0: michael@0: void appendCallSite(const CallSiteDesc &desc) { michael@0: enoughMemory_ &= append(CallSite(desc, currentOffset(), framePushed_)); michael@0: } michael@0: michael@0: void call(const CallSiteDesc &desc, const Register reg) { michael@0: call(reg); michael@0: appendCallSite(desc); michael@0: } michael@0: void call(const CallSiteDesc &desc, Label *label) { michael@0: call(label); michael@0: appendCallSite(desc); michael@0: } michael@0: void call(const CallSiteDesc &desc, AsmJSImmPtr imm) { michael@0: call(imm); michael@0: appendCallSite(desc); michael@0: } michael@0: void callExit(AsmJSImmPtr imm, uint32_t stackArgBytes) { michael@0: movePtr(imm, CallReg); michael@0: ma_callAndStoreRet(CallReg, stackArgBytes); michael@0: appendCallSite(CallSiteDesc::Exit()); michael@0: } michael@0: void callIonFromAsmJS(const Register reg) { michael@0: ma_callIonNoPush(reg); michael@0: appendCallSite(CallSiteDesc::Exit()); michael@0: michael@0: // The Ion ABI has the callee pop the return address off the stack. michael@0: // The asm.js caller assumes that the call leaves sp unchanged, so bump michael@0: // the stack. michael@0: subPtr(Imm32(sizeof(void*)), sp); michael@0: } michael@0: michael@0: void branch(JitCode *c) { michael@0: BufferOffset bo = m_buffer.nextOffset(); michael@0: addPendingJump(bo, ImmPtr(c->raw()), Relocation::JITCODE); michael@0: RelocStyle rs; michael@0: if (hasMOVWT()) michael@0: rs = L_MOVWT; michael@0: else michael@0: rs = L_LDR; michael@0: michael@0: ma_movPatchable(ImmPtr(c->raw()), ScratchRegister, Always, rs); michael@0: ma_bx(ScratchRegister); michael@0: } michael@0: void branch(const Register reg) { michael@0: ma_bx(reg); michael@0: } michael@0: void nop() { michael@0: ma_nop(); michael@0: } michael@0: void ret() { michael@0: ma_pop(pc); michael@0: m_buffer.markGuard(); michael@0: } michael@0: void retn(Imm32 n) { michael@0: // pc <- [sp]; sp += n michael@0: ma_dtr(IsLoad, sp, n, pc, PostIndex); michael@0: m_buffer.markGuard(); michael@0: } michael@0: void push(Imm32 imm) { michael@0: ma_mov(imm, ScratchRegister); michael@0: ma_push(ScratchRegister); michael@0: } michael@0: void push(ImmWord imm) { michael@0: push(Imm32(imm.value)); michael@0: } michael@0: void push(ImmGCPtr imm) { michael@0: ma_mov(imm, ScratchRegister); michael@0: ma_push(ScratchRegister); michael@0: } michael@0: void push(const Address &address) { michael@0: ma_ldr(Operand(address.base, address.offset), ScratchRegister); michael@0: ma_push(ScratchRegister); michael@0: } michael@0: void push(const Register ®) { michael@0: ma_push(reg); michael@0: } michael@0: void push(const FloatRegister ®) { michael@0: ma_vpush(VFPRegister(reg)); michael@0: } michael@0: void pushWithPadding(const Register ®, const Imm32 extraSpace) { michael@0: Imm32 totSpace = Imm32(extraSpace.value + 4); michael@0: ma_dtr(IsStore, sp, totSpace, reg, PreIndex); michael@0: } michael@0: void pushWithPadding(const Imm32 &imm, const Imm32 extraSpace) { michael@0: Imm32 totSpace = Imm32(extraSpace.value + 4); michael@0: // ma_dtr may need the scratch register to adjust the stack, so use the michael@0: // second scratch register. michael@0: ma_mov(imm, secondScratchReg_); michael@0: ma_dtr(IsStore, sp, totSpace, secondScratchReg_, PreIndex); michael@0: } michael@0: michael@0: void pop(const Register ®) { michael@0: ma_pop(reg); michael@0: } michael@0: void pop(const FloatRegister ®) { michael@0: ma_vpop(VFPRegister(reg)); michael@0: } michael@0: michael@0: void popN(const Register ®, Imm32 extraSpace) { michael@0: Imm32 totSpace = Imm32(extraSpace.value + 4); michael@0: ma_dtr(IsLoad, sp, totSpace, reg, PostIndex); michael@0: } michael@0: michael@0: CodeOffsetLabel toggledJump(Label *label); michael@0: michael@0: // Emit a BLX or NOP instruction. ToggleCall can be used to patch michael@0: // this instruction. michael@0: CodeOffsetLabel toggledCall(JitCode *target, bool enabled); michael@0: michael@0: static size_t ToggledCallSize() { michael@0: if (hasMOVWT()) michael@0: // Size of a movw, movt, nop/blx instruction. michael@0: return 12; michael@0: // Size of a ldr, nop/blx instruction michael@0: return 8; michael@0: } michael@0: michael@0: CodeOffsetLabel pushWithPatch(ImmWord imm) { michael@0: CodeOffsetLabel label = movWithPatch(imm, ScratchRegister); michael@0: ma_push(ScratchRegister); michael@0: return label; michael@0: } michael@0: michael@0: CodeOffsetLabel movWithPatch(ImmWord imm, Register dest) { michael@0: CodeOffsetLabel label = currentOffset(); michael@0: ma_movPatchable(Imm32(imm.value), dest, Always, hasMOVWT() ? L_MOVWT : L_LDR); michael@0: return label; michael@0: } michael@0: CodeOffsetLabel movWithPatch(ImmPtr imm, Register dest) { michael@0: return movWithPatch(ImmWord(uintptr_t(imm.value)), dest); michael@0: } michael@0: michael@0: void jump(Label *label) { michael@0: as_b(label); michael@0: } michael@0: void jump(Register reg) { michael@0: ma_bx(reg); michael@0: } michael@0: void jump(const Address &address) { michael@0: ma_ldr(Operand(address.base, address.offset), ScratchRegister); michael@0: ma_bx(ScratchRegister); michael@0: } michael@0: michael@0: void neg32(Register reg) { michael@0: ma_neg(reg, reg, SetCond); michael@0: } michael@0: void negl(Register reg) { michael@0: ma_neg(reg, reg, SetCond); michael@0: } michael@0: void test32(Register lhs, Register rhs) { michael@0: ma_tst(lhs, rhs); michael@0: } michael@0: void test32(Register lhs, Imm32 imm) { michael@0: ma_tst(lhs, imm); michael@0: } michael@0: void test32(const Address &address, Imm32 imm) { michael@0: ma_ldr(Operand(address.base, address.offset), ScratchRegister); michael@0: ma_tst(ScratchRegister, imm); michael@0: } michael@0: void testPtr(Register lhs, Register rhs) { michael@0: test32(lhs, rhs); michael@0: } michael@0: michael@0: // Returns the register containing the type tag. michael@0: Register splitTagForTest(const ValueOperand &value) { michael@0: return value.typeReg(); michael@0: } michael@0: michael@0: // higher level tag testing code michael@0: Condition testInt32(Condition cond, const ValueOperand &value); michael@0: Condition testBoolean(Condition cond, const ValueOperand &value); michael@0: Condition testDouble(Condition cond, const ValueOperand &value); michael@0: Condition testNull(Condition cond, const ValueOperand &value); michael@0: Condition testUndefined(Condition cond, const ValueOperand &value); michael@0: Condition testString(Condition cond, const ValueOperand &value); michael@0: Condition testObject(Condition cond, const ValueOperand &value); michael@0: Condition testNumber(Condition cond, const ValueOperand &value); michael@0: Condition testMagic(Condition cond, const ValueOperand &value); michael@0: michael@0: Condition testPrimitive(Condition cond, const ValueOperand &value); michael@0: michael@0: // register-based tests michael@0: Condition testInt32(Condition cond, const Register &tag); michael@0: Condition testBoolean(Condition cond, const Register &tag); michael@0: Condition testNull(Condition cond, const Register &tag); michael@0: Condition testUndefined(Condition cond, const Register &tag); michael@0: Condition testString(Condition cond, const Register &tag); michael@0: Condition testObject(Condition cond, const Register &tag); michael@0: Condition testDouble(Condition cond, const Register &tag); michael@0: Condition testNumber(Condition cond, const Register &tag); michael@0: Condition testMagic(Condition cond, const Register &tag); michael@0: Condition testPrimitive(Condition cond, const Register &tag); michael@0: michael@0: Condition testGCThing(Condition cond, const Address &address); michael@0: Condition testMagic(Condition cond, const Address &address); michael@0: Condition testInt32(Condition cond, const Address &address); michael@0: Condition testDouble(Condition cond, const Address &address); michael@0: Condition testBoolean(Condition cond, const Address &address); michael@0: Condition testNull(Condition cond, const Address &address); michael@0: Condition testUndefined(Condition cond, const Address &address); michael@0: Condition testString(Condition cond, const Address &address); michael@0: Condition testObject(Condition cond, const Address &address); michael@0: Condition testNumber(Condition cond, const Address &address); michael@0: michael@0: Condition testUndefined(Condition cond, const BaseIndex &src); michael@0: Condition testNull(Condition cond, const BaseIndex &src); michael@0: Condition testBoolean(Condition cond, const BaseIndex &src); michael@0: Condition testString(Condition cond, const BaseIndex &src); michael@0: Condition testInt32(Condition cond, const BaseIndex &src); michael@0: Condition testObject(Condition cond, const BaseIndex &src); michael@0: Condition testDouble(Condition cond, const BaseIndex &src); michael@0: Condition testMagic(Condition cond, const BaseIndex &src); michael@0: Condition testGCThing(Condition cond, const BaseIndex &src); michael@0: michael@0: template michael@0: void branchTestGCThing(Condition cond, const T &t, Label *label) { michael@0: Condition c = testGCThing(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestPrimitive(Condition cond, const T &t, Label *label) { michael@0: Condition c = testPrimitive(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: michael@0: void branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label); michael@0: void branchTestValue(Condition cond, const Address &valaddr, const ValueOperand &value, michael@0: Label *label); michael@0: michael@0: // unboxing code michael@0: void unboxInt32(const ValueOperand &operand, const Register &dest); michael@0: void unboxInt32(const Address &src, const Register &dest); michael@0: void unboxBoolean(const ValueOperand &operand, const Register &dest); michael@0: void unboxBoolean(const Address &src, const Register &dest); michael@0: void unboxDouble(const ValueOperand &operand, const FloatRegister &dest); michael@0: void unboxDouble(const Address &src, const FloatRegister &dest); michael@0: void unboxString(const ValueOperand &operand, const Register &dest); michael@0: void unboxString(const Address &src, const Register &dest); michael@0: void unboxObject(const ValueOperand &src, const Register &dest); michael@0: void unboxValue(const ValueOperand &src, AnyRegister dest); michael@0: void unboxPrivate(const ValueOperand &src, Register dest); michael@0: michael@0: void notBoolean(const ValueOperand &val) { michael@0: ma_eor(Imm32(1), val.payloadReg()); michael@0: } michael@0: michael@0: // boxing code michael@0: void boxDouble(const FloatRegister &src, const ValueOperand &dest); michael@0: void boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest); michael@0: michael@0: // Extended unboxing API. If the payload is already in a register, returns michael@0: // that register. Otherwise, provides a move to the given scratch register, michael@0: // and returns that. michael@0: Register extractObject(const Address &address, Register scratch); michael@0: Register extractObject(const ValueOperand &value, Register scratch) { michael@0: return value.payloadReg(); michael@0: } michael@0: Register extractInt32(const ValueOperand &value, Register scratch) { michael@0: return value.payloadReg(); michael@0: } michael@0: Register extractBoolean(const ValueOperand &value, Register scratch) { michael@0: return value.payloadReg(); michael@0: } michael@0: Register extractTag(const Address &address, Register scratch); michael@0: Register extractTag(const BaseIndex &address, Register scratch); michael@0: Register extractTag(const ValueOperand &value, Register scratch) { michael@0: return value.typeReg(); michael@0: } michael@0: michael@0: void boolValueToDouble(const ValueOperand &operand, const FloatRegister &dest); michael@0: void int32ValueToDouble(const ValueOperand &operand, const FloatRegister &dest); michael@0: void loadInt32OrDouble(const Operand &src, const FloatRegister &dest); michael@0: void loadInt32OrDouble(Register base, Register index, michael@0: const FloatRegister &dest, int32_t shift = defaultShift); michael@0: void loadConstantDouble(double dp, const FloatRegister &dest); michael@0: // treat the value as a boolean, and set condition codes accordingly michael@0: Condition testInt32Truthy(bool truthy, const ValueOperand &operand); michael@0: Condition testBooleanTruthy(bool truthy, const ValueOperand &operand); michael@0: Condition testDoubleTruthy(bool truthy, const FloatRegister ®); michael@0: Condition testStringTruthy(bool truthy, const ValueOperand &value); michael@0: michael@0: void boolValueToFloat32(const ValueOperand &operand, const FloatRegister &dest); michael@0: void int32ValueToFloat32(const ValueOperand &operand, const FloatRegister &dest); michael@0: void loadConstantFloat32(float f, const FloatRegister &dest); michael@0: michael@0: template michael@0: void branchTestInt32(Condition cond, const T & t, Label *label) { michael@0: Condition c = testInt32(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestBoolean(Condition cond, const T & t, Label *label) { michael@0: Condition c = testBoolean(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: void branch32(Condition cond, Register lhs, Register rhs, Label *label) { michael@0: ma_cmp(lhs, rhs); michael@0: ma_b(label, cond); michael@0: } michael@0: void branch32(Condition cond, Register lhs, Imm32 imm, Label *label) { michael@0: ma_cmp(lhs, imm); michael@0: ma_b(label, cond); michael@0: } michael@0: void branch32(Condition cond, const Operand &lhs, Register rhs, Label *label) { michael@0: if (lhs.getTag() == Operand::OP2) { michael@0: branch32(cond, lhs.toReg(), rhs, label); michael@0: } else { michael@0: ma_ldr(lhs, ScratchRegister); michael@0: branch32(cond, ScratchRegister, rhs, label); michael@0: } michael@0: } michael@0: void branch32(Condition cond, const Operand &lhs, Imm32 rhs, Label *label) { michael@0: if (lhs.getTag() == Operand::OP2) { michael@0: branch32(cond, lhs.toReg(), rhs, label); michael@0: } else { michael@0: // branch32 will use ScratchRegister. michael@0: ma_ldr(lhs, secondScratchReg_); michael@0: branch32(cond, secondScratchReg_, rhs, label); michael@0: } michael@0: } michael@0: void branch32(Condition cond, const Address &lhs, Register rhs, Label *label) { michael@0: load32(lhs, ScratchRegister); michael@0: branch32(cond, ScratchRegister, rhs, label); michael@0: } michael@0: void branch32(Condition cond, const Address &lhs, Imm32 rhs, Label *label) { michael@0: // branch32 will use ScratchRegister. michael@0: load32(lhs, secondScratchReg_); michael@0: branch32(cond, secondScratchReg_, rhs, label); michael@0: } michael@0: void branchPtr(Condition cond, const Address &lhs, Register rhs, Label *label) { michael@0: branch32(cond, lhs, rhs, label); michael@0: } michael@0: michael@0: void branchPrivatePtr(Condition cond, const Address &lhs, ImmPtr ptr, Label *label) { michael@0: branchPtr(cond, lhs, ptr, label); michael@0: } michael@0: michael@0: void branchPrivatePtr(Condition cond, const Address &lhs, Register ptr, Label *label) { michael@0: branchPtr(cond, lhs, ptr, label); michael@0: } michael@0: michael@0: void branchPrivatePtr(Condition cond, Register lhs, ImmWord ptr, Label *label) { michael@0: branchPtr(cond, lhs, ptr, label); michael@0: } michael@0: michael@0: template michael@0: void branchTestDouble(Condition cond, const T & t, Label *label) { michael@0: Condition c = testDouble(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestNull(Condition cond, const T & t, Label *label) { michael@0: Condition c = testNull(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestObject(Condition cond, const T & t, Label *label) { michael@0: Condition c = testObject(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestString(Condition cond, const T & t, Label *label) { michael@0: Condition c = testString(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestUndefined(Condition cond, const T & t, Label *label) { michael@0: Condition c = testUndefined(cond, t); michael@0: ma_b(label, c); michael@0: } michael@0: template michael@0: void branchTestNumber(Condition cond, const T &t, Label *label) { michael@0: cond = testNumber(cond, t); michael@0: ma_b(label, cond); michael@0: } michael@0: template michael@0: void branchTestMagic(Condition cond, const T &t, Label *label) { michael@0: cond = testMagic(cond, t); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchTestMagicValue(Condition cond, const ValueOperand &val, JSWhyMagic why, michael@0: Label *label) { michael@0: JS_ASSERT(cond == Equal || cond == NotEqual); michael@0: // Test for magic michael@0: Label notmagic; michael@0: Condition testCond = testMagic(cond, val); michael@0: ma_b(¬magic, InvertCondition(testCond)); michael@0: // Test magic value michael@0: branch32(cond, val.payloadReg(), Imm32(static_cast(why)), label); michael@0: bind(¬magic); michael@0: } michael@0: void branchTestInt32Truthy(bool truthy, const ValueOperand &operand, Label *label) { michael@0: Condition c = testInt32Truthy(truthy, operand); michael@0: ma_b(label, c); michael@0: } michael@0: void branchTestBooleanTruthy(bool truthy, const ValueOperand &operand, Label *label) { michael@0: Condition c = testBooleanTruthy(truthy, operand); michael@0: ma_b(label, c); michael@0: } michael@0: void branchTestDoubleTruthy(bool truthy, const FloatRegister ®, Label *label) { michael@0: Condition c = testDoubleTruthy(truthy, reg); michael@0: ma_b(label, c); michael@0: } michael@0: void branchTestStringTruthy(bool truthy, const ValueOperand &value, Label *label) { michael@0: Condition c = testStringTruthy(truthy, value); michael@0: ma_b(label, c); michael@0: } michael@0: void branchTest32(Condition cond, const Register &lhs, const Register &rhs, Label *label) { michael@0: // x86 likes test foo, foo rather than cmp foo, #0. michael@0: // Convert the former into the latter. michael@0: if (lhs == rhs && (cond == Zero || cond == NonZero)) michael@0: ma_cmp(lhs, Imm32(0)); michael@0: else michael@0: ma_tst(lhs, rhs); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchTest32(Condition cond, const Register &lhs, Imm32 imm, Label *label) { michael@0: ma_tst(lhs, imm); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchTest32(Condition cond, const Address &address, Imm32 imm, Label *label) { michael@0: // branchTest32 will use ScratchRegister. michael@0: load32(address, secondScratchReg_); michael@0: branchTest32(cond, secondScratchReg_, imm, label); michael@0: } michael@0: void branchTestPtr(Condition cond, const Register &lhs, const Register &rhs, Label *label) { michael@0: branchTest32(cond, lhs, rhs, label); michael@0: } michael@0: void branchTestPtr(Condition cond, const Register &lhs, const Imm32 rhs, Label *label) { michael@0: branchTest32(cond, lhs, rhs, label); michael@0: } michael@0: void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) { michael@0: branchTest32(cond, lhs, imm, label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, Register rhs, Label *label) { michael@0: branch32(cond, lhs, rhs, label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, ImmGCPtr ptr, Label *label) { michael@0: movePtr(ptr, ScratchRegister); michael@0: branchPtr(cond, lhs, ScratchRegister, label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, ImmWord imm, Label *label) { michael@0: branch32(cond, lhs, Imm32(imm.value), label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, ImmPtr imm, Label *label) { michael@0: branchPtr(cond, lhs, ImmWord(uintptr_t(imm.value)), label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, AsmJSImmPtr imm, Label *label) { michael@0: movePtr(imm, ScratchRegister); michael@0: branchPtr(cond, lhs, ScratchRegister, label); michael@0: } michael@0: void branchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) { michael@0: branch32(cond, lhs, imm, label); michael@0: } michael@0: void decBranchPtr(Condition cond, const Register &lhs, Imm32 imm, Label *label) { michael@0: subPtr(imm, lhs); michael@0: branch32(cond, lhs, Imm32(0), label); michael@0: } michael@0: void moveValue(const Value &val, Register type, Register data); michael@0: michael@0: CodeOffsetJump jumpWithPatch(RepatchLabel *label, Condition cond = Always); michael@0: template michael@0: CodeOffsetJump branchPtrWithPatch(Condition cond, Register reg, T ptr, RepatchLabel *label) { michael@0: ma_cmp(reg, ptr); michael@0: return jumpWithPatch(label, cond); michael@0: } michael@0: template michael@0: CodeOffsetJump branchPtrWithPatch(Condition cond, Address addr, T ptr, RepatchLabel *label) { michael@0: ma_ldr(addr, secondScratchReg_); michael@0: ma_cmp(secondScratchReg_, ptr); michael@0: return jumpWithPatch(label, cond); michael@0: } michael@0: void branchPtr(Condition cond, Address addr, ImmGCPtr ptr, Label *label) { michael@0: ma_ldr(addr, secondScratchReg_); michael@0: ma_cmp(secondScratchReg_, ptr); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchPtr(Condition cond, Address addr, ImmWord ptr, Label *label) { michael@0: ma_ldr(addr, secondScratchReg_); michael@0: ma_cmp(secondScratchReg_, ptr); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchPtr(Condition cond, Address addr, ImmPtr ptr, Label *label) { michael@0: branchPtr(cond, addr, ImmWord(uintptr_t(ptr.value)), label); michael@0: } michael@0: void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) { michael@0: loadPtr(addr, ScratchRegister); michael@0: ma_cmp(ScratchRegister, ptr); michael@0: ma_b(label, cond); michael@0: } michael@0: void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, const Register &ptr, Label *label) { michael@0: loadPtr(addr, ScratchRegister); michael@0: ma_cmp(ScratchRegister, ptr); michael@0: ma_b(label, cond); michael@0: } michael@0: void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) { michael@0: loadPtr(lhs, secondScratchReg_); // ma_cmp will use the scratch register. michael@0: ma_cmp(secondScratchReg_, rhs); michael@0: ma_b(label, cond); michael@0: } michael@0: void branch32(Condition cond, const AbsoluteAddress &lhs, const Register &rhs, Label *label) { michael@0: loadPtr(lhs, secondScratchReg_); // ma_cmp will use the scratch register. michael@0: ma_cmp(secondScratchReg_, rhs); michael@0: ma_b(label, cond); michael@0: } michael@0: michael@0: void loadUnboxedValue(Address address, MIRType type, AnyRegister dest) { michael@0: if (dest.isFloat()) michael@0: loadInt32OrDouble(Operand(address), dest.fpu()); michael@0: else michael@0: ma_ldr(address, dest.gpr()); michael@0: } michael@0: michael@0: void loadUnboxedValue(BaseIndex address, MIRType type, AnyRegister dest) { michael@0: if (dest.isFloat()) michael@0: loadInt32OrDouble(address.base, address.index, dest.fpu(), address.scale); michael@0: else michael@0: load32(address, dest.gpr()); michael@0: } michael@0: michael@0: void moveValue(const Value &val, const ValueOperand &dest); michael@0: michael@0: void moveValue(const ValueOperand &src, const ValueOperand &dest) { michael@0: Register s0 = src.typeReg(), d0 = dest.typeReg(), michael@0: s1 = src.payloadReg(), d1 = dest.payloadReg(); michael@0: michael@0: // Either one or both of the source registers could be the same as a michael@0: // destination register. michael@0: if (s1 == d0) { michael@0: if (s0 == d1) { michael@0: // If both are, this is just a swap of two registers. michael@0: JS_ASSERT(d1 != ScratchRegister); michael@0: JS_ASSERT(d0 != ScratchRegister); michael@0: ma_mov(d1, ScratchRegister); michael@0: ma_mov(d0, d1); michael@0: ma_mov(ScratchRegister, d0); michael@0: return; michael@0: } michael@0: // If only one is, copy that source first. michael@0: mozilla::Swap(s0, s1); michael@0: mozilla::Swap(d0, d1); michael@0: } michael@0: michael@0: if (s0 != d0) michael@0: ma_mov(s0, d0); michael@0: if (s1 != d1) michael@0: ma_mov(s1, d1); michael@0: } michael@0: michael@0: void storeValue(ValueOperand val, Operand dst); michael@0: void storeValue(ValueOperand val, const BaseIndex &dest); michael@0: void storeValue(JSValueType type, Register reg, BaseIndex dest) { michael@0: // Harder cases not handled yet. michael@0: JS_ASSERT(dest.offset == 0); michael@0: ma_alu(dest.base, lsl(dest.index, dest.scale), ScratchRegister, op_add); michael@0: storeValue(type, reg, Address(ScratchRegister, 0)); michael@0: } michael@0: void storeValue(ValueOperand val, const Address &dest) { michael@0: storeValue(val, Operand(dest)); michael@0: } michael@0: void storeValue(JSValueType type, Register reg, Address dest) { michael@0: ma_str(reg, dest); michael@0: ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), secondScratchReg_); michael@0: ma_str(secondScratchReg_, Address(dest.base, dest.offset + 4)); michael@0: } michael@0: void storeValue(const Value &val, Address dest) { michael@0: jsval_layout jv = JSVAL_TO_IMPL(val); michael@0: ma_mov(Imm32(jv.s.tag), secondScratchReg_); michael@0: ma_str(secondScratchReg_, Address(dest.base, dest.offset + 4)); michael@0: if (val.isMarkable()) michael@0: ma_mov(ImmGCPtr(reinterpret_cast(val.toGCThing())), secondScratchReg_); michael@0: else michael@0: ma_mov(Imm32(jv.s.payload.i32), secondScratchReg_); michael@0: ma_str(secondScratchReg_, dest); michael@0: } michael@0: void storeValue(const Value &val, BaseIndex dest) { michael@0: // Harder cases not handled yet. michael@0: JS_ASSERT(dest.offset == 0); michael@0: ma_alu(dest.base, lsl(dest.index, dest.scale), ScratchRegister, op_add); michael@0: storeValue(val, Address(ScratchRegister, 0)); michael@0: } michael@0: michael@0: void loadValue(Address src, ValueOperand val); michael@0: void loadValue(Operand dest, ValueOperand val) { michael@0: loadValue(dest.toAddress(), val); michael@0: } michael@0: void loadValue(const BaseIndex &addr, ValueOperand val); michael@0: void tagValue(JSValueType type, Register payload, ValueOperand dest); michael@0: michael@0: void pushValue(ValueOperand val); michael@0: void popValue(ValueOperand val); michael@0: void pushValue(const Value &val) { michael@0: jsval_layout jv = JSVAL_TO_IMPL(val); michael@0: push(Imm32(jv.s.tag)); michael@0: if (val.isMarkable()) michael@0: push(ImmGCPtr(reinterpret_cast(val.toGCThing()))); michael@0: else michael@0: push(Imm32(jv.s.payload.i32)); michael@0: } michael@0: void pushValue(JSValueType type, Register reg) { michael@0: push(ImmTag(JSVAL_TYPE_TO_TAG(type))); michael@0: ma_push(reg); michael@0: } michael@0: void pushValue(const Address &addr); michael@0: void Push(const ValueOperand &val) { michael@0: pushValue(val); michael@0: framePushed_ += sizeof(Value); michael@0: } michael@0: void Pop(const ValueOperand &val) { michael@0: popValue(val); michael@0: framePushed_ -= sizeof(Value); michael@0: } michael@0: void storePayload(const Value &val, Operand dest); michael@0: void storePayload(Register src, Operand dest); michael@0: void storePayload(const Value &val, Register base, Register index, int32_t shift = defaultShift); michael@0: void storePayload(Register src, Register base, Register index, int32_t shift = defaultShift); michael@0: void storeTypeTag(ImmTag tag, Operand dest); michael@0: void storeTypeTag(ImmTag tag, Register base, Register index, int32_t shift = defaultShift); michael@0: michael@0: void makeFrameDescriptor(Register frameSizeReg, FrameType type) { michael@0: ma_lsl(Imm32(FRAMESIZE_SHIFT), frameSizeReg, frameSizeReg); michael@0: ma_orr(Imm32(type), frameSizeReg); michael@0: } michael@0: michael@0: void linkExitFrame(); michael@0: void linkParallelExitFrame(const Register &pt); michael@0: void handleFailureWithHandler(void *handler); michael@0: void handleFailureWithHandlerTail(); michael@0: michael@0: ///////////////////////////////////////////////////////////////// michael@0: // Common interface. michael@0: ///////////////////////////////////////////////////////////////// michael@0: public: michael@0: // The following functions are exposed for use in platform-shared code. michael@0: void Push(const Register ®) { michael@0: ma_push(reg); michael@0: adjustFrame(sizeof(intptr_t)); michael@0: } michael@0: void Push(const Imm32 imm) { michael@0: push(imm); michael@0: adjustFrame(sizeof(intptr_t)); michael@0: } michael@0: void Push(const ImmWord imm) { michael@0: push(imm); michael@0: adjustFrame(sizeof(intptr_t)); michael@0: } michael@0: void Push(const ImmPtr imm) { michael@0: Push(ImmWord(uintptr_t(imm.value))); michael@0: } michael@0: void Push(const ImmGCPtr ptr) { michael@0: push(ptr); michael@0: adjustFrame(sizeof(intptr_t)); michael@0: } michael@0: void Push(const FloatRegister &t) { michael@0: VFPRegister r = VFPRegister(t); michael@0: ma_vpush(VFPRegister(t)); michael@0: adjustFrame(r.size()); michael@0: } michael@0: michael@0: CodeOffsetLabel PushWithPatch(const ImmWord &word) { michael@0: framePushed_ += sizeof(word.value); michael@0: return pushWithPatch(word); michael@0: } michael@0: CodeOffsetLabel PushWithPatch(const ImmPtr &imm) { michael@0: return PushWithPatch(ImmWord(uintptr_t(imm.value))); michael@0: } michael@0: michael@0: void PushWithPadding(const Register ®, const Imm32 extraSpace) { michael@0: pushWithPadding(reg, extraSpace); michael@0: adjustFrame(sizeof(intptr_t) + extraSpace.value); michael@0: } michael@0: void PushWithPadding(const Imm32 imm, const Imm32 extraSpace) { michael@0: pushWithPadding(imm, extraSpace); michael@0: adjustFrame(sizeof(intptr_t) + extraSpace.value); michael@0: } michael@0: michael@0: void Pop(const Register ®) { michael@0: ma_pop(reg); michael@0: adjustFrame(-sizeof(intptr_t)); michael@0: } michael@0: void implicitPop(uint32_t args) { michael@0: JS_ASSERT(args % sizeof(intptr_t) == 0); michael@0: adjustFrame(-args); michael@0: } michael@0: uint32_t framePushed() const { michael@0: return framePushed_; michael@0: } michael@0: void setFramePushed(uint32_t framePushed) { michael@0: framePushed_ = framePushed; michael@0: } michael@0: michael@0: // Builds an exit frame on the stack, with a return address to an internal michael@0: // non-function. Returns offset to be passed to markSafepointAt(). michael@0: bool buildFakeExitFrame(const Register &scratch, uint32_t *offset); michael@0: michael@0: void callWithExitFrame(JitCode *target); michael@0: void callWithExitFrame(JitCode *target, Register dynStack); michael@0: michael@0: // Makes an Ion call using the only two methods that it is sane for michael@0: // indep code to make a call michael@0: void callIon(const Register &callee); michael@0: michael@0: void reserveStack(uint32_t amount); michael@0: void freeStack(uint32_t amount); michael@0: void freeStack(Register amount); michael@0: michael@0: void add32(Register src, Register dest); michael@0: void add32(Imm32 imm, Register dest); michael@0: void add32(Imm32 imm, const Address &dest); michael@0: void sub32(Imm32 imm, Register dest); michael@0: void sub32(Register src, Register dest); michael@0: template michael@0: void branchAdd32(Condition cond, T src, Register dest, Label *label) { michael@0: add32(src, dest); michael@0: j(cond, label); michael@0: } michael@0: template michael@0: void branchSub32(Condition cond, T src, Register dest, Label *label) { michael@0: sub32(src, dest); michael@0: j(cond, label); michael@0: } michael@0: void xor32(Imm32 imm, Register dest); michael@0: michael@0: void and32(Imm32 imm, Register dest); michael@0: void and32(Imm32 imm, const Address &dest); michael@0: void or32(Imm32 imm, const Address &dest); michael@0: void xorPtr(Imm32 imm, Register dest); michael@0: void xorPtr(Register src, Register dest); michael@0: void orPtr(Imm32 imm, Register dest); michael@0: void orPtr(Register src, Register dest); michael@0: void andPtr(Imm32 imm, Register dest); michael@0: void andPtr(Register src, Register dest); michael@0: void addPtr(Register src, Register dest); michael@0: void addPtr(const Address &src, Register dest); michael@0: void not32(Register reg); michael@0: michael@0: void move32(const Imm32 &imm, const Register &dest); michael@0: void move32(const Register &src, const Register &dest); michael@0: michael@0: void movePtr(const Register &src, const Register &dest); michael@0: void movePtr(const ImmWord &imm, const Register &dest); michael@0: void movePtr(const ImmPtr &imm, const Register &dest); michael@0: void movePtr(const AsmJSImmPtr &imm, const Register &dest); michael@0: void movePtr(const ImmGCPtr &imm, const Register &dest); michael@0: michael@0: void load8SignExtend(const Address &address, const Register &dest); michael@0: void load8SignExtend(const BaseIndex &src, const Register &dest); michael@0: michael@0: void load8ZeroExtend(const Address &address, const Register &dest); michael@0: void load8ZeroExtend(const BaseIndex &src, const Register &dest); michael@0: michael@0: void load16SignExtend(const Address &address, const Register &dest); michael@0: void load16SignExtend(const BaseIndex &src, const Register &dest); michael@0: michael@0: void load16ZeroExtend(const Address &address, const Register &dest); michael@0: void load16ZeroExtend(const BaseIndex &src, const Register &dest); michael@0: michael@0: void load32(const Address &address, const Register &dest); michael@0: void load32(const BaseIndex &address, const Register &dest); michael@0: void load32(const AbsoluteAddress &address, const Register &dest); michael@0: michael@0: void loadPtr(const Address &address, const Register &dest); michael@0: void loadPtr(const BaseIndex &src, const Register &dest); michael@0: void loadPtr(const AbsoluteAddress &address, const Register &dest); michael@0: void loadPtr(const AsmJSAbsoluteAddress &address, const Register &dest); michael@0: michael@0: void loadPrivate(const Address &address, const Register &dest); michael@0: michael@0: void loadDouble(const Address &addr, const FloatRegister &dest); michael@0: void loadDouble(const BaseIndex &src, const FloatRegister &dest); michael@0: michael@0: // Load a float value into a register, then expand it to a double. michael@0: void loadFloatAsDouble(const Address &addr, const FloatRegister &dest); michael@0: void loadFloatAsDouble(const BaseIndex &src, const FloatRegister &dest); michael@0: michael@0: void loadFloat32(const Address &addr, const FloatRegister &dest); michael@0: void loadFloat32(const BaseIndex &src, const FloatRegister &dest); michael@0: michael@0: void store8(const Register &src, const Address &address); michael@0: void store8(const Imm32 &imm, const Address &address); michael@0: void store8(const Register &src, const BaseIndex &address); michael@0: void store8(const Imm32 &imm, const BaseIndex &address); michael@0: michael@0: void store16(const Register &src, const Address &address); michael@0: void store16(const Imm32 &imm, const Address &address); michael@0: void store16(const Register &src, const BaseIndex &address); michael@0: void store16(const Imm32 &imm, const BaseIndex &address); michael@0: michael@0: void store32(const Register &src, const AbsoluteAddress &address); michael@0: void store32(const Register &src, const Address &address); michael@0: void store32(const Register &src, const BaseIndex &address); michael@0: void store32(const Imm32 &src, const Address &address); michael@0: void store32(const Imm32 &src, const BaseIndex &address); michael@0: michael@0: void storePtr(ImmWord imm, const Address &address); michael@0: void storePtr(ImmPtr imm, const Address &address); michael@0: void storePtr(ImmGCPtr imm, const Address &address); michael@0: void storePtr(Register src, const Address &address); michael@0: void storePtr(const Register &src, const AbsoluteAddress &dest); michael@0: void storeDouble(FloatRegister src, Address addr) { michael@0: ma_vstr(src, Operand(addr)); michael@0: } michael@0: void storeDouble(FloatRegister src, BaseIndex addr) { michael@0: // Harder cases not handled yet. michael@0: JS_ASSERT(addr.offset == 0); michael@0: uint32_t scale = Imm32::ShiftOf(addr.scale).value; michael@0: ma_vstr(src, addr.base, addr.index, scale); michael@0: } michael@0: void moveDouble(FloatRegister src, FloatRegister dest) { michael@0: ma_vmov(src, dest); michael@0: } michael@0: michael@0: void storeFloat32(FloatRegister src, Address addr) { michael@0: ma_vstr(VFPRegister(src).singleOverlay(), Operand(addr)); michael@0: } michael@0: void storeFloat32(FloatRegister src, BaseIndex addr) { michael@0: // Harder cases not handled yet. michael@0: JS_ASSERT(addr.offset == 0); michael@0: uint32_t scale = Imm32::ShiftOf(addr.scale).value; michael@0: ma_vstr(VFPRegister(src).singleOverlay(), addr.base, addr.index, scale); michael@0: } michael@0: michael@0: void clampIntToUint8(Register reg) { michael@0: // look at (reg >> 8) if it is 0, then reg shouldn't be clamped michael@0: // if it is <0, then we want to clamp to 0, otherwise, we wish to clamp to 255 michael@0: as_mov(ScratchRegister, asr(reg, 8), SetCond); michael@0: ma_mov(Imm32(0xff), reg, NoSetCond, NotEqual); michael@0: ma_mov(Imm32(0), reg, NoSetCond, Signed); michael@0: } michael@0: michael@0: void cmp32(const Register &lhs, const Imm32 &rhs); michael@0: void cmp32(const Register &lhs, const Register &rhs); michael@0: void cmp32(const Operand &lhs, const Imm32 &rhs); michael@0: void cmp32(const Operand &lhs, const Register &rhs); michael@0: michael@0: void cmpPtr(const Register &lhs, const ImmWord &rhs); michael@0: void cmpPtr(const Register &lhs, const ImmPtr &rhs); michael@0: void cmpPtr(const Register &lhs, const Register &rhs); michael@0: void cmpPtr(const Register &lhs, const ImmGCPtr &rhs); michael@0: void cmpPtr(const Register &lhs, const Imm32 &rhs); michael@0: void cmpPtr(const Address &lhs, const Register &rhs); michael@0: void cmpPtr(const Address &lhs, const ImmWord &rhs); michael@0: void cmpPtr(const Address &lhs, const ImmPtr &rhs); michael@0: michael@0: void subPtr(Imm32 imm, const Register dest); michael@0: void subPtr(const Address &addr, const Register dest); michael@0: void subPtr(const Register &src, const Register &dest); michael@0: void subPtr(const Register &src, const Address &dest); michael@0: void addPtr(Imm32 imm, const Register dest); michael@0: void addPtr(Imm32 imm, const Address &dest); michael@0: void addPtr(ImmWord imm, const Register dest) { michael@0: addPtr(Imm32(imm.value), dest); michael@0: } michael@0: void addPtr(ImmPtr imm, const Register dest) { michael@0: addPtr(ImmWord(uintptr_t(imm.value)), dest); michael@0: } michael@0: michael@0: void setStackArg(const Register ®, uint32_t arg); michael@0: michael@0: void breakpoint(); michael@0: // conditional breakpoint michael@0: void breakpoint(Condition cc); michael@0: michael@0: void compareDouble(FloatRegister lhs, FloatRegister rhs); michael@0: void branchDouble(DoubleCondition cond, const FloatRegister &lhs, const FloatRegister &rhs, michael@0: Label *label); michael@0: michael@0: void compareFloat(FloatRegister lhs, FloatRegister rhs); michael@0: void branchFloat(DoubleCondition cond, const FloatRegister &lhs, const FloatRegister &rhs, michael@0: Label *label); michael@0: michael@0: void checkStackAlignment(); michael@0: michael@0: void rshiftPtr(Imm32 imm, Register dest) { michael@0: ma_lsr(imm, dest, dest); michael@0: } michael@0: void lshiftPtr(Imm32 imm, Register dest) { michael@0: ma_lsl(imm, dest, dest); michael@0: } michael@0: michael@0: // If source is a double, load it into dest. If source is int32, michael@0: // convert it to double. Else, branch to failure. michael@0: void ensureDouble(const ValueOperand &source, FloatRegister dest, Label *failure); michael@0: michael@0: void michael@0: emitSet(Assembler::Condition cond, const Register &dest) michael@0: { michael@0: ma_mov(Imm32(0), dest); michael@0: ma_mov(Imm32(1), dest, NoSetCond, cond); michael@0: } michael@0: michael@0: template michael@0: void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest) michael@0: { michael@0: cmpPtr(lhs, rhs); michael@0: emitSet(cond, dest); michael@0: } michael@0: template michael@0: void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest) michael@0: { michael@0: cmp32(lhs, rhs); michael@0: emitSet(cond, dest); michael@0: } michael@0: michael@0: void testNullSet(Condition cond, const ValueOperand &value, Register dest) { michael@0: cond = testNull(cond, value); michael@0: emitSet(cond, dest); michael@0: } michael@0: void testUndefinedSet(Condition cond, const ValueOperand &value, Register dest) { michael@0: cond = testUndefined(cond, value); michael@0: emitSet(cond, dest); michael@0: } michael@0: michael@0: // Setup a call to C/C++ code, given the number of general arguments it michael@0: // takes. Note that this only supports cdecl. michael@0: // michael@0: // In order for alignment to work correctly, the MacroAssembler must have a michael@0: // consistent view of the stack displacement. It is okay to call "push" michael@0: // manually, however, if the stack alignment were to change, the macro michael@0: // assembler should be notified before starting a call. michael@0: void setupAlignedABICall(uint32_t args); michael@0: michael@0: // Sets up an ABI call for when the alignment is not known. This may need a michael@0: // scratch register. michael@0: void setupUnalignedABICall(uint32_t args, const Register &scratch); michael@0: michael@0: // Arguments must be assigned in a left-to-right order. This process may michael@0: // temporarily use more stack, in which case esp-relative addresses will be michael@0: // automatically adjusted. It is extremely important that esp-relative michael@0: // addresses are computed *after* setupABICall(). Furthermore, no michael@0: // operations should be emitted while setting arguments. michael@0: void passABIArg(const MoveOperand &from, MoveOp::Type type); michael@0: void passABIArg(const Register ®); michael@0: void passABIArg(const FloatRegister ®, MoveOp::Type type); michael@0: void passABIArg(const ValueOperand ®s); michael@0: michael@0: private: michael@0: void passHardFpABIArg(const MoveOperand &from, MoveOp::Type type); michael@0: void passSoftFpABIArg(const MoveOperand &from, MoveOp::Type type); michael@0: michael@0: protected: michael@0: bool buildOOLFakeExitFrame(void *fakeReturnAddr); michael@0: michael@0: private: michael@0: void callWithABIPre(uint32_t *stackAdjust); michael@0: void callWithABIPost(uint32_t stackAdjust, MoveOp::Type result); michael@0: michael@0: public: michael@0: // Emits a call to a C/C++ function, resolving all argument moves. michael@0: void callWithABI(void *fun, MoveOp::Type result = MoveOp::GENERAL); michael@0: void callWithABI(AsmJSImmPtr imm, MoveOp::Type result = MoveOp::GENERAL); michael@0: void callWithABI(const Address &fun, MoveOp::Type result = MoveOp::GENERAL); michael@0: michael@0: CodeOffsetLabel labelForPatch() { michael@0: return CodeOffsetLabel(nextOffset().getOffset()); michael@0: } michael@0: michael@0: void computeEffectiveAddress(const Address &address, Register dest) { michael@0: ma_add(address.base, Imm32(address.offset), dest, NoSetCond); michael@0: } michael@0: void computeEffectiveAddress(const BaseIndex &address, Register dest) { michael@0: ma_alu(address.base, lsl(address.index, address.scale), dest, op_add, NoSetCond); michael@0: if (address.offset) michael@0: ma_add(dest, Imm32(address.offset), dest, NoSetCond); michael@0: } michael@0: void floor(FloatRegister input, Register output, Label *handleNotAnInt); michael@0: void floorf(FloatRegister input, Register output, Label *handleNotAnInt); michael@0: void round(FloatRegister input, Register output, Label *handleNotAnInt, FloatRegister tmp); michael@0: void roundf(FloatRegister input, Register output, Label *handleNotAnInt, FloatRegister tmp); michael@0: michael@0: void clampCheck(Register r, Label *handleNotAnInt) { michael@0: // check explicitly for r == INT_MIN || r == INT_MAX michael@0: // this is the instruction sequence that gcc generated for this michael@0: // operation. michael@0: ma_sub(r, Imm32(0x80000001), ScratchRegister); michael@0: ma_cmn(ScratchRegister, Imm32(3)); michael@0: ma_b(handleNotAnInt, Above); michael@0: } michael@0: michael@0: void memIntToValue(Address Source, Address Dest) { michael@0: load32(Source, lr); michael@0: storeValue(JSVAL_TYPE_INT32, lr, Dest); michael@0: } michael@0: void memMove32(Address Source, Address Dest) { michael@0: loadPtr(Source, lr); michael@0: storePtr(lr, Dest); michael@0: } michael@0: void memMove64(Address Source, Address Dest) { michael@0: loadPtr(Source, lr); michael@0: storePtr(lr, Dest); michael@0: loadPtr(Address(Source.base, Source.offset+4), lr); michael@0: storePtr(lr, Address(Dest.base, Dest.offset+4)); michael@0: } michael@0: michael@0: void lea(Operand addr, Register dest) { michael@0: ma_add(addr.baseReg(), Imm32(addr.disp()), dest); michael@0: } michael@0: michael@0: void stackCheck(ImmWord limitAddr, Label *label) { michael@0: int *foo = 0; michael@0: *foo = 5; michael@0: movePtr(limitAddr, ScratchRegister); michael@0: ma_ldr(Address(ScratchRegister, 0), ScratchRegister); michael@0: ma_cmp(ScratchRegister, StackPointer); michael@0: ma_b(label, Assembler::AboveOrEqual); michael@0: } michael@0: void abiret() { michael@0: as_bx(lr); michael@0: } michael@0: michael@0: void ma_storeImm(Imm32 c, const Operand &dest) { michael@0: ma_mov(c, lr); michael@0: ma_str(lr, dest); michael@0: } michael@0: BufferOffset ma_BoundsCheck(Register bounded) { michael@0: return as_cmp(bounded, Imm8(0)); michael@0: } michael@0: michael@0: void moveFloat32(FloatRegister src, FloatRegister dest) { michael@0: as_vmov(VFPRegister(dest).singleOverlay(), VFPRegister(src).singleOverlay()); michael@0: } michael@0: michael@0: #ifdef JSGC_GENERATIONAL michael@0: void branchPtrInNurseryRange(Register ptr, Register temp, Label *label); michael@0: void branchValueIsNurseryObject(ValueOperand value, Register temp, Label *label); michael@0: #endif michael@0: }; michael@0: michael@0: typedef MacroAssemblerARMCompat MacroAssemblerSpecific; michael@0: michael@0: } // namespace jit michael@0: } // namespace js michael@0: michael@0: #endif /* jit_arm_MacroAssembler_arm_h */