michael@0: #include "ia32_modrm.h"
michael@0: #include "ia32_reg.h"
michael@0: #include "x86_imm.h"
michael@0: 
michael@0: /* NOTE: when decoding ModR/M and SIB, we have to add 1 to all register
michael@0:  * values obtained from decoding the ModR/M or SIB byte, since they
michael@0:  * are encoded with eAX = 0 and the tables in ia32_reg.c use eAX = 1.
michael@0:  * ADDENDUM: this is only the case when the register value is used
michael@0:  * directly as an index into the register table, not when it is added to
michael@0:  * a genregs offset. */
michael@0: 
michael@0: /* -------------------------------- ModR/M, SIB */
michael@0: /* ModR/M flags */
michael@0: #define MODRM_RM_SIB            0x04    /* R/M == 100 */
michael@0: #define MODRM_RM_NOREG          0x05    /* R/B == 101 */
michael@0: 
michael@0: /* if (MODRM.MOD_NODISP && MODRM.RM_NOREG) then just disp32 */
michael@0: #define MODRM_MOD_NODISP        0x00    /* mod == 00 */
michael@0: #define MODRM_MOD_DISP8         0x01    /* mod == 01 */
michael@0: #define MODRM_MOD_DISP32        0x02    /* mod == 10 */
michael@0: #define MODRM_MOD_NOEA          0x03    /* mod == 11 */
michael@0: 
michael@0: /* 16-bit modrm flags */
michael@0: #define MOD16_MOD_NODISP      0
michael@0: #define MOD16_MOD_DISP8       1
michael@0: #define MOD16_MOD_DISP16      2
michael@0: #define MOD16_MOD_REG         3
michael@0: 
michael@0: #define MOD16_RM_BXSI         0
michael@0: #define MOD16_RM_BXDI         1
michael@0: #define MOD16_RM_BPSI         2
michael@0: #define MOD16_RM_BPDI         3
michael@0: #define MOD16_RM_SI           4
michael@0: #define MOD16_RM_DI           5
michael@0: #define MOD16_RM_BP           6
michael@0: #define MOD16_RM_BX           7
michael@0: 
michael@0: /* SIB flags */
michael@0: #define SIB_INDEX_NONE       0x04
michael@0: #define SIB_BASE_EBP       0x05
michael@0: #define SIB_SCALE_NOBASE    0x00
michael@0: 
michael@0: /* Convenience struct for modR/M bitfield */
michael@0: struct modRM_byte {  
michael@0:    unsigned int mod : 2;
michael@0:    unsigned int reg : 3;
michael@0:    unsigned int rm  : 3; 
michael@0: };
michael@0: 
michael@0: /* Convenience struct for SIB bitfield */
michael@0: struct SIB_byte {
michael@0:    unsigned int scale : 2;
michael@0:    unsigned int index : 3;
michael@0:    unsigned int base  : 3;
michael@0: };
michael@0: 
michael@0: 
michael@0: #if 0
michael@0: int modrm_rm[] = {0,1,2,3,MODRM_RM_SIB,MODRM_MOD_DISP32,6,7};
michael@0: int modrm_reg[] = {0, 1, 2, 3, 4, 5, 6, 7};
michael@0: int modrm_mod[]  = {0, MODRM_MOD_DISP8, MODRM_MOD_DISP32, MODRM_MOD_NOEA};
michael@0: int sib_scl[] = {0, 2, 4, 8};
michael@0: int sib_idx[] = {0, 1, 2, 3, SIB_INDEX_NONE, 5, 6, 7 };
michael@0: int sib_bas[] = {0, 1, 2, 3, 4, SIB_SCALE_NOBASE, 6, 7 };
michael@0: #endif
michael@0: 
michael@0: /* this is needed to replace x86_imm_signsized() which does not sign-extend
michael@0:  * to dest */
michael@0: static unsigned int imm32_signsized( unsigned char *buf, size_t buf_len,
michael@0: 				     int32_t *dest, unsigned int size ) {
michael@0: 	if ( size > buf_len ) {
michael@0: 		return 0;
michael@0: 	}
michael@0: 
michael@0: 	switch (size) {
michael@0: 		case 1:
michael@0: 			*dest = *((signed char *) buf);
michael@0: 			break;
michael@0: 		case 2:
michael@0: 			*dest = *((signed short *) buf);
michael@0: 			break;
michael@0: 		case 4:
michael@0: 		default:
michael@0: 			*dest = *((signed int *) buf);
michael@0: 			break;
michael@0: 	}
michael@0: 
michael@0: 	return size;
michael@0: }
michael@0: 
michael@0: 
michael@0: 
michael@0: static void byte_decode(unsigned char b, struct modRM_byte *modrm) {
michael@0: 	/* generic bitfield-packing routine */
michael@0: 
michael@0: 	modrm->mod = b >> 6;	/* top 2 bits */
michael@0: 	modrm->reg = (b & 56) >> 3;	/* middle 3 bits */
michael@0: 	modrm->rm = b & 7;	/* bottom 3 bits */
michael@0: }
michael@0: 
michael@0: 
michael@0: static size_t sib_decode( unsigned char *buf, size_t buf_len, x86_ea_t *ea, 
michael@0: 			  unsigned int mod ) {
michael@0: 	/* set Address Expression fields (scale, index, base, disp) 
michael@0: 	 * according to the contents of the SIB byte.
michael@0: 	 *  b points to the SIB byte in the instruction-stream buffer; the
michael@0: 	 *    byte after b[0] is therefore the byte after the SIB
michael@0: 	 *  returns number of bytes 'used', including the SIB byte */
michael@0: 	size_t size = 1;		/* start at 1 for SIB byte */
michael@0: 	struct SIB_byte sib;
michael@0: 
michael@0: 	if ( buf_len < 1 ) {
michael@0: 		return 0;
michael@0: 	}
michael@0: 
michael@0: 	byte_decode( *buf, (struct modRM_byte *)(void*)&sib );  /* get bit-fields */
michael@0: 
michael@0: 	if ( sib.base == SIB_BASE_EBP && ! mod ) {  /* if base == 101 (ebp) */
michael@0: 	    /* IF BASE == EBP, deal with exception */
michael@0: 		/* IF (ModR/M did not create a Disp */
michael@0: 		/* ... create a 32-bit Displacement */
michael@0: 		imm32_signsized( &buf[1], buf_len, &ea->disp, sizeof(int32_t));
michael@0: 		ea->disp_size = sizeof(int32_t);
michael@0: 		ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 		size += 4;	/* add sizeof disp to count */
michael@0: 
michael@0: 	} else {
michael@0: 		/* ELSE BASE refers to a General Register */
michael@0: 		ia32_handle_register( &ea->base, sib.base + 1 );
michael@0: 	}
michael@0: 
michael@0: 	/* set scale to 1, 2, 4, 8 */
michael@0: 	ea->scale = 1 << sib.scale;
michael@0: 
michael@0: 	if (sib.index != SIB_INDEX_NONE) {
michael@0: 		/* IF INDEX is not 'ESP' (100) */
michael@0: 		ia32_handle_register( &ea->index, sib.index + 1 );
michael@0: 	}
michael@0: 
michael@0: 	return (size);		/* return number of bytes processed */
michael@0: }
michael@0: 
michael@0: static size_t modrm_decode16( unsigned char *buf, unsigned int buf_len,
michael@0: 			    x86_op_t *op, struct modRM_byte *modrm ) {
michael@0: 	/* 16-bit mode: hackish, but not as hackish as 32-bit mode ;) */
michael@0: 	size_t size = 1; /* # of bytes decoded [1 for modR/M byte] */
michael@0: 	x86_ea_t * ea = &op->data.expression;
michael@0: 
michael@0: 	switch( modrm->rm ) {
michael@0: 		case MOD16_RM_BXSI:
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 3);
michael@0: 			ia32_handle_register(&ea->index, REG_WORD_OFFSET + 6);
michael@0: 			break;
michael@0: 		case MOD16_RM_BXDI:
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 3);
michael@0: 			ia32_handle_register(&ea->index, REG_WORD_OFFSET + 7);
michael@0: 		case MOD16_RM_BPSI:
michael@0: 			op->flags |= op_ss_seg;
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 5);
michael@0: 			ia32_handle_register(&ea->index, REG_WORD_OFFSET + 6);
michael@0: 			break;
michael@0: 		case MOD16_RM_BPDI:
michael@0: 			op->flags |= op_ss_seg;
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 5);
michael@0: 			ia32_handle_register(&ea->index, REG_WORD_OFFSET + 7);
michael@0: 			break;
michael@0: 		case MOD16_RM_SI:
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 6);
michael@0: 			break;
michael@0: 		case MOD16_RM_DI:
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 7);
michael@0: 			break;
michael@0: 		case MOD16_RM_BP:
michael@0: 			if ( modrm->mod != MOD16_MOD_NODISP ) {
michael@0: 				op->flags |= op_ss_seg;
michael@0: 				ia32_handle_register(&ea->base, 
michael@0: 						     REG_WORD_OFFSET + 5);
michael@0: 			}
michael@0: 			break;
michael@0: 		case MOD16_RM_BX:
michael@0: 			ia32_handle_register(&ea->base, REG_WORD_OFFSET + 3);
michael@0: 			break;
michael@0: 	}
michael@0: 
michael@0: 	/* move to byte after ModR/M */
michael@0: 	++buf;
michael@0: 	--buf_len;
michael@0: 
michael@0: 	if ( modrm->mod == MOD16_MOD_DISP8 ) {
michael@0: 		imm32_signsized( buf, buf_len, &ea->disp, sizeof(char) );
michael@0: 		ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 		ea->disp_size = sizeof(char);
michael@0: 		size += sizeof(char);
michael@0: 	} else if ( modrm->mod == MOD16_MOD_DISP16 ) {
michael@0: 		imm32_signsized( buf, buf_len, &ea->disp, sizeof(short) );
michael@0: 		ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 		ea->disp_size = sizeof(short);
michael@0: 		size += sizeof(short);
michael@0: 	} 
michael@0: 
michael@0: 	return size;
michael@0: }
michael@0: 
michael@0: /* TODO : Mark index modes
michael@0:     Use addressing mode flags to imply arrays (index), structure (disp),
michael@0:     two-dimensional arrays [disp + index], classes [ea reg], and so on.
michael@0: */
michael@0: size_t ia32_modrm_decode( unsigned char *buf, unsigned int buf_len,
michael@0: 			    x86_op_t *op, x86_insn_t *insn, size_t gen_regs ) {
michael@0: 	/* create address expression and/or fill operand based on value of
michael@0: 	 * ModR/M byte. Calls sib_decode as appropriate.
michael@0: 	 *    flags specifies whether Reg or mod+R/M fields are being decoded
michael@0: 	 *  returns the number of bytes in the instruction, including modR/M */
michael@0: 	struct modRM_byte modrm;
michael@0: 	size_t size = 1;	/* # of bytes decoded [1 for modR/M byte] */
michael@0: 	x86_ea_t * ea;
michael@0: 
michael@0: 
michael@0: 	byte_decode(*buf, &modrm);	/* get bitfields */
michael@0: 
michael@0: 	/* first, handle the case where the mod field is a register only */
michael@0: 	if ( modrm.mod == MODRM_MOD_NOEA ) {
michael@0: 		op->type = op_register;
michael@0: 		ia32_handle_register(&op->data.reg, modrm.rm + gen_regs);
michael@0:                 /* increase insn size by 1 for modrm byte */
michael@0:  		return 1;
michael@0:  	}
michael@0:  
michael@0: 	/* then deal with cases where there is an effective address */
michael@0: 	ea = &op->data.expression;
michael@0: 	op->type = op_expression;
michael@0: 	op->flags |= op_pointer;
michael@0: 
michael@0: 	if ( insn->addr_size == 2 ) {
michael@0: 		/* gah! 16 bit mode! */
michael@0: 		return modrm_decode16( buf, buf_len, op, &modrm);
michael@0: 	}
michael@0: 
michael@0: 	/* move to byte after ModR/M */
michael@0: 	++buf;
michael@0: 	--buf_len;
michael@0: 
michael@0: 	if (modrm.mod == MODRM_MOD_NODISP) {	/* if mod == 00 */
michael@0: 
michael@0: 		/* IF MOD == No displacement, just Indirect Register */
michael@0: 		if (modrm.rm == MODRM_RM_NOREG) {	/* if r/m == 101 */
michael@0: 			/* IF RM == No Register, just Displacement */
michael@0: 			/* This is an Intel Moronic Exception TM */
michael@0: 			imm32_signsized( buf, buf_len, &ea->disp, 
michael@0: 					sizeof(int32_t) );
michael@0: 			ea->disp_size = sizeof(int32_t);
michael@0: 			ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 			size += 4;	/* add sizeof disp to count */
michael@0: 
michael@0: 		} else if (modrm.rm == MODRM_RM_SIB) {	/* if r/m == 100 */
michael@0: 			/* ELSE IF an SIB byte is present */
michael@0: 			/* TODO: check for 0 retval */
michael@0: 			size += sib_decode( buf, buf_len, ea, modrm.mod);
michael@0: 			/* move to byte after SIB for displacement */
michael@0: 			++buf;
michael@0: 			--buf_len;
michael@0: 		} else {	/* modR/M specifies base register */
michael@0: 			/* ELSE RM encodes a general register */
michael@0: 			ia32_handle_register( &ea->base, modrm.rm + 1 );
michael@0: 		}
michael@0: 	} else { 					/* mod is 01 or 10 */
michael@0: 		if (modrm.rm == MODRM_RM_SIB) {	/* rm == 100 */
michael@0: 			/* IF base is an AddrExpr specified by an SIB byte */
michael@0: 			/* TODO: check for 0 retval */
michael@0: 			size += sib_decode( buf, buf_len, ea, modrm.mod);
michael@0: 			/* move to byte after SIB for displacement */
michael@0: 			++buf;
michael@0: 			--buf_len;
michael@0: 		} else {
michael@0: 			/* ELSE base is a general register */
michael@0: 			ia32_handle_register( &ea->base, modrm.rm + 1 );
michael@0: 		}
michael@0: 
michael@0: 		/* ELSE mod + r/m specify a disp##[base] or disp##(SIB) */
michael@0: 		if (modrm.mod == MODRM_MOD_DISP8) {		/* mod == 01 */
michael@0: 			/* If this is an 8-bit displacement */
michael@0: 			imm32_signsized( buf, buf_len, &ea->disp, 
michael@0: 					sizeof(char));
michael@0: 			ea->disp_size = sizeof(char);
michael@0: 			ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 			size += 1;	/* add sizeof disp to count */
michael@0: 
michael@0: 		} else {
michael@0: 			/* Displacement is dependent on address size */
michael@0: 			imm32_signsized( buf, buf_len, &ea->disp, 
michael@0: 					insn->addr_size);
michael@0: 			ea->disp_size = insn->addr_size;
michael@0: 			ea->disp_sign = (ea->disp < 0) ? 1 : 0;
michael@0: 			size += 4;
michael@0: 		}
michael@0: 	}
michael@0: 
michael@0: 	return size;		/* number of bytes found in instruction */
michael@0: }
michael@0: 
michael@0: void ia32_reg_decode( unsigned char byte, x86_op_t *op, size_t gen_regs ) {
michael@0: 	struct modRM_byte modrm;
michael@0: 	byte_decode( byte, &modrm );	/* get bitfields */
michael@0: 
michael@0:  	/* set operand to register ID */
michael@0: 	op->type = op_register;
michael@0: 	ia32_handle_register(&op->data.reg, modrm.reg + gen_regs);
michael@0: 
michael@0: 	return;
michael@0: }