michael@0: #ifndef __LINUX_TAVARUA_H
michael@0: #define __LINUX_TAVARUA_H
michael@0: 
michael@0: /* This is a Linux header generated by "make headers_install" */
michael@0: 
michael@0: #include <stdint.h>
michael@0: #include <linux/ioctl.h>
michael@0: #include <linux/videodev2.h>
michael@0: 
michael@0: 
michael@0: #undef FM_DEBUG
michael@0: 
michael@0: /* constants */
michael@0: #define  RDS_BLOCKS_NUM             (4)
michael@0: #define BYTES_PER_BLOCK             (3)
michael@0: #define MAX_PS_LENGTH              (96)
michael@0: #define MAX_RT_LENGTH              (64)
michael@0: 
michael@0: #define XFRDAT0                    (0x20)
michael@0: #define XFRDAT1                    (0x21)
michael@0: #define XFRDAT2                    (0x22)
michael@0: 
michael@0: #define INTDET_PEEK_MSB            (0x88)
michael@0: #define INTDET_PEEK_LSB            (0x26)
michael@0: 
michael@0: #define RMSSI_PEEK_MSB             (0x88)
michael@0: #define RMSSI_PEEK_LSB             (0xA8)
michael@0: 
michael@0: #define MPX_DCC_BYPASS_POKE_MSB    (0x88)
michael@0: #define MPX_DCC_BYPASS_POKE_LSB    (0xC0)
michael@0: 
michael@0: #define MPX_DCC_PEEK_MSB_REG1      (0x88)
michael@0: #define MPX_DCC_PEEK_LSB_REG1      (0xC2)
michael@0: 
michael@0: #define MPX_DCC_PEEK_MSB_REG2      (0x88)
michael@0: #define MPX_DCC_PEEK_LSB_REG2      (0xC3)
michael@0: 
michael@0: #define MPX_DCC_PEEK_MSB_REG3      (0x88)
michael@0: #define MPX_DCC_PEEK_LSB_REG3      (0xC4)
michael@0: 
michael@0: #define ON_CHANNEL_TH_MSB          (0x0B)
michael@0: #define ON_CHANNEL_TH_LSB          (0xA8)
michael@0: 
michael@0: #define OFF_CHANNEL_TH_MSB         (0x0B)
michael@0: #define OFF_CHANNEL_TH_LSB         (0xAC)
michael@0: 
michael@0: #define ENF_200Khz                    (1)
michael@0: #define SRCH200KHZ_OFFSET             (7)
michael@0: #define SRCH_MASK                  (1 << SRCH200KHZ_OFFSET)
michael@0: 
michael@0: /* Standard buffer size */
michael@0: #define STD_BUF_SIZE               (128)
michael@0: /* Search direction */
michael@0: #define SRCH_DIR_UP                 (0)
michael@0: #define SRCH_DIR_DOWN               (1)
michael@0: 
michael@0: /* control options */
michael@0: #define CTRL_ON                     (1)
michael@0: #define CTRL_OFF                    (0)
michael@0: 
michael@0: #define US_LOW_BAND                (87.5)
michael@0: #define US_HIGH_BAND               (108)
michael@0: 
michael@0: /* constant for Tx */
michael@0: 
michael@0: #define MASK_PI                    (0x0000FFFF)
michael@0: #define MASK_PI_MSB                (0x0000FF00)
michael@0: #define MASK_PI_LSB                (0x000000FF)
michael@0: #define MASK_PTY                   (0x0000001F)
michael@0: #define MASK_TXREPCOUNT            (0x0000000F)
michael@0: 
michael@0: #undef FMDBG
michael@0: #ifdef FM_DEBUG
michael@0:   #define FMDBG(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
michael@0: #else
michael@0:   #define FMDBG(fmt, args...)
michael@0: #endif
michael@0: 
michael@0: #undef FMDERR
michael@0: #define FMDERR(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
michael@0: 
michael@0: #undef FMDBG_I2C
michael@0: #ifdef FM_DEBUG_I2C
michael@0:   #define FMDBG_I2C(fmt, args...) printk(KERN_INFO "fm_i2c: " fmt, ##args)
michael@0: #else
michael@0:   #define FMDBG_I2C(fmt, args...)
michael@0: #endif
michael@0: 
michael@0: /* function declarations */
michael@0: /* FM Core audio paths. */
michael@0: #define TAVARUA_AUDIO_OUT_ANALOG_OFF	(0)
michael@0: #define TAVARUA_AUDIO_OUT_ANALOG_ON	(1)
michael@0: #define TAVARUA_AUDIO_OUT_DIGITAL_OFF	(0)
michael@0: #define TAVARUA_AUDIO_OUT_DIGITAL_ON	(1)
michael@0: 
michael@0: int tavarua_set_audio_path(int digital_on, int analog_on);
michael@0: 
michael@0: /* defines and enums*/
michael@0: 
michael@0: #define MARIMBA_A0	0x01010013
michael@0: #define MARIMBA_2_1	0x02010204
michael@0: #define BAHAMA_1_0	0x0302010A
michael@0: #define BAHAMA_2_0	0x04020205
michael@0: #define WAIT_TIMEOUT 2000
michael@0: #define RADIO_INIT_TIME 15
michael@0: #define TAVARUA_DELAY 10
michael@0: /*
michael@0:  * The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
michael@0:  * 62.5 kHz otherwise.
michael@0:  * The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
michael@0:  * tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
michael@0:  * The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
michael@0:  */
michael@0: #define FREQ_MUL (1000000 / 62.5)
michael@0: 
michael@0: enum v4l2_cid_private_tavarua_t {
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCHMODE = (V4L2_CID_PRIVATE_BASE + 1),
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SCANDWELL,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCHON,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_STATE,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_TRANSMIT_MODE,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_REGION,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCH_PI,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_EMPHASIS,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RDS_STD,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SPACING,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RDSON,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_LP_MODE,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_ANTENNA,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_PSALL,
michael@0: 	/*v4l2 Tx controls*/
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_IOVERC,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_INTDET,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_MPX_DCC,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_AF_JUMP,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_RSSI_DELTA,
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_HLSI,
michael@0: 
michael@0: 	/*
michael@0: 	* Here we have IOCTl's that are specific to IRIS
michael@0: 	* (V4L2_CID_PRIVATE_BASE + 0x1E to V4L2_CID_PRIVATE_BASE + 0x28)
michael@0: 	*/
michael@0: 	V4L2_CID_PRIVATE_SOFT_MUTE,/* 0x800001E*/
michael@0: 	V4L2_CID_PRIVATE_RIVA_ACCS_ADDR,
michael@0: 	V4L2_CID_PRIVATE_RIVA_ACCS_LEN,
michael@0: 	V4L2_CID_PRIVATE_RIVA_PEEK,
michael@0: 	V4L2_CID_PRIVATE_RIVA_POKE,
michael@0: 	V4L2_CID_PRIVATE_SSBI_ACCS_ADDR,
michael@0: 	V4L2_CID_PRIVATE_SSBI_PEEK,
michael@0: 	V4L2_CID_PRIVATE_SSBI_POKE,
michael@0: 	V4L2_CID_PRIVATE_TX_TONE,
michael@0: 	V4L2_CID_PRIVATE_RDS_GRP_COUNTERS,
michael@0: 	V4L2_CID_PRIVATE_SET_NOTCH_FILTER,/* 0x8000028 */
michael@0: 
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH,/* 0x8000029 */
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_DO_CALIBRATION,/* 0x800002A : IRIS */
michael@0: 	V4L2_CID_PRIVATE_TAVARUA_SRCH_ALGORITHM,/* 0x800002B */
michael@0: 	V4L2_CID_PRIVATE_IRIS_GET_SINR, /* 0x800002C : IRIS */
michael@0: 	V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, /* 0x800002D */
michael@0: 	V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, /* 0x800002E */
michael@0: 	V4L2_CID_PRIVATE_SINR_THRESHOLD,  /* 0x800002F : IRIS */
michael@0: 	V4L2_CID_PRIVATE_SINR_SAMPLES,  /* 0x8000030 : IRIS */
michael@0: 
michael@0: };
michael@0: 
michael@0: enum tavarua_buf_t {
michael@0: 	TAVARUA_BUF_SRCH_LIST,
michael@0: 	TAVARUA_BUF_EVENTS,
michael@0: 	TAVARUA_BUF_RT_RDS,
michael@0: 	TAVARUA_BUF_PS_RDS,
michael@0: 	TAVARUA_BUF_RAW_RDS,
michael@0: 	TAVARUA_BUF_AF_LIST,
michael@0: 	TAVARUA_BUF_MAX
michael@0: };
michael@0: 
michael@0: enum tavarua_xfr_t {
michael@0: 	TAVARUA_XFR_SYNC,
michael@0: 	TAVARUA_XFR_ERROR,
michael@0: 	TAVARUA_XFR_SRCH_LIST,
michael@0: 	TAVARUA_XFR_RT_RDS,
michael@0: 	TAVARUA_XFR_PS_RDS,
michael@0: 	TAVARUA_XFR_AF_LIST,
michael@0: 	TAVARUA_XFR_MAX
michael@0: };
michael@0: 
michael@0: enum channel_spacing {
michael@0: 	FM_CH_SPACE_200KHZ,
michael@0: 	FM_CH_SPACE_100KHZ,
michael@0: 	FM_CH_SPACE_50KHZ
michael@0: };
michael@0: 
michael@0: enum step_size {
michael@0: 	NO_SRCH200khz,
michael@0: 	ENF_SRCH200khz
michael@0: };
michael@0: 
michael@0: enum emphasis {
michael@0: 	EMP_75,
michael@0: 	EMP_50
michael@0: };
michael@0: 
michael@0: enum rds_std {
michael@0: 	RBDS_STD,
michael@0: 	RDS_STD
michael@0: };
michael@0: 
michael@0: /* offsets */
michael@0: #define RAW_RDS		0x0F
michael@0: #define RDS_BLOCK 	3
michael@0: 
michael@0: /* registers*/
michael@0: #define MARIMBA_XO_BUFF_CNTRL 0x07
michael@0: #define RADIO_REGISTERS 0x30
michael@0: #define XFR_REG_NUM     16
michael@0: #define STATUS_REG_NUM 	3
michael@0: 
michael@0: /* TX constants */
michael@0: #define HEADER_SIZE	4
michael@0: #define TX_ON		0x80
michael@0: #define TAVARUA_TX_RT	RDS_RT_0
michael@0: #define TAVARUA_TX_PS	RDS_PS_0
michael@0: 
michael@0: enum register_t {
michael@0: 	STATUS_REG1 = 0,
michael@0: 	STATUS_REG2,
michael@0: 	STATUS_REG3,
michael@0: 	RDCTRL,
michael@0: 	FREQ,
michael@0: 	TUNECTRL,
michael@0: 	SRCHRDS1,
michael@0: 	SRCHRDS2,
michael@0: 	SRCHCTRL,
michael@0: 	IOCTRL,
michael@0: 	RDSCTRL,
michael@0: 	ADVCTRL,
michael@0: 	AUDIOCTRL,
michael@0: 	RMSSI,
michael@0: 	IOVERC,
michael@0: 	AUDIOIND = 0x1E,
michael@0: 	XFRCTRL,
michael@0: 	FM_CTL0 = 0xFF,
michael@0: 	LEAKAGE_CNTRL = 0xFE,
michael@0: };
michael@0: #define BAHAMA_RBIAS_CTL1       0x07
michael@0: #define	BAHAMA_FM_MODE_REG      0xFD
michael@0: #define	BAHAMA_FM_CTL1_REG      0xFE
michael@0: #define	BAHAMA_FM_CTL0_REG      0xFF
michael@0: #define BAHAMA_FM_MODE_NORMAL   0x00
michael@0: #define BAHAMA_LDO_DREG_CTL0    0xF0
michael@0: #define BAHAMA_LDO_AREG_CTL0    0xF4
michael@0: 
michael@0: /* Radio Control */
michael@0: #define RDCTRL_STATE_OFFSET	0
michael@0: #define RDCTRL_STATE_MASK	(3 << RDCTRL_STATE_OFFSET)
michael@0: #define RDCTRL_BAND_OFFSET	2
michael@0: #define RDCTRL_BAND_MASK	(1 << RDCTRL_BAND_OFFSET)
michael@0: #define RDCTRL_CHSPACE_OFFSET	3
michael@0: #define RDCTRL_CHSPACE_MASK	(3 << RDCTRL_CHSPACE_OFFSET)
michael@0: #define RDCTRL_DEEMPHASIS_OFFSET 5
michael@0: #define RDCTRL_DEEMPHASIS_MASK	(1 << RDCTRL_DEEMPHASIS_OFFSET)
michael@0: #define RDCTRL_HLSI_OFFSET	6
michael@0: #define RDCTRL_HLSI_MASK	(3 << RDCTRL_HLSI_OFFSET)
michael@0: #define RDSAF_OFFSET		6
michael@0: #define RDSAF_MASK		(1 << RDSAF_OFFSET)
michael@0: 
michael@0: /* Tune Control */
michael@0: #define TUNE_STATION	0x01
michael@0: #define ADD_OFFSET	(1 << 1)
michael@0: #define SIGSTATE	(1 << 5)
michael@0: #define MOSTSTATE	(1 << 6)
michael@0: #define RDSSYNC		(1 << 7)
michael@0: /* Search Control */
michael@0: #define SRCH_MODE_OFFSET	0
michael@0: #define SRCH_MODE_MASK		(7 << SRCH_MODE_OFFSET)
michael@0: #define SRCH_DIR_OFFSET		3
michael@0: #define SRCH_DIR_MASK		(1 << SRCH_DIR_OFFSET)
michael@0: #define SRCH_DWELL_OFFSET	4
michael@0: #define SRCH_DWELL_MASK		(7 << SRCH_DWELL_OFFSET)
michael@0: #define SRCH_STATE_OFFSET	7
michael@0: #define SRCH_STATE_MASK		(1 << SRCH_STATE_OFFSET)
michael@0: 
michael@0: /* I/O Control */
michael@0: #define IOC_HRD_MUTE	0x03
michael@0: #define IOC_SFT_MUTE    (1 << 2)
michael@0: #define IOC_MON_STR     (1 << 3)
michael@0: #define IOC_SIG_BLND    (1 << 4)
michael@0: #define IOC_INTF_BLND   (1 << 5)
michael@0: #define IOC_ANTENNA     (1 << 6)
michael@0: #define IOC_ANTENNA_OFFSET	6
michael@0: #define IOC_ANTENNA_MASK     	(1 << IOC_ANTENNA_OFFSET)
michael@0: 
michael@0: /* RDS Control */
michael@0: #define RDS_ON		0x01
michael@0: #define RDSCTRL_STANDARD_OFFSET 1
michael@0: #define RDSCTRL_STANDARD_MASK	(1 << RDSCTRL_STANDARD_OFFSET)
michael@0: 
michael@0: /* Advanced features controls */
michael@0: #define RDSRTEN		(1 << 3)
michael@0: #define RDSPSEN		(1 << 4)
michael@0: 
michael@0: /* Audio path control */
michael@0: #define AUDIORX_ANALOG_OFFSET 	0
michael@0: #define AUDIORX_ANALOG_MASK 	(1 << AUDIORX_ANALOG_OFFSET)
michael@0: #define AUDIORX_DIGITAL_OFFSET 	1
michael@0: #define AUDIORX_DIGITAL_MASK 	(1 << AUDIORX_DIGITAL_OFFSET)
michael@0: #define AUDIOTX_OFFSET		2
michael@0: #define AUDIOTX_MASK		(1 << AUDIOTX_OFFSET)
michael@0: #define I2SCTRL_OFFSET		3
michael@0: #define I2SCTRL_MASK		(1 << I2SCTRL_OFFSET)
michael@0: 
michael@0: /* Search options */
michael@0: enum search_t {
michael@0: 	SEEK,
michael@0: 	SCAN,
michael@0: 	SCAN_FOR_STRONG,
michael@0: 	SCAN_FOR_WEAK,
michael@0: 	RDS_SEEK_PTY,
michael@0: 	RDS_SCAN_PTY,
michael@0: 	RDS_SEEK_PI,
michael@0: 	RDS_AF_JUMP,
michael@0: };
michael@0: 
michael@0: enum audio_path {
michael@0: 	FM_DIGITAL_PATH,
michael@0: 	FM_ANALOG_PATH
michael@0: };
michael@0: #define SRCH_MODE	0x07
michael@0: #define SRCH_DIR	0x08 /* 0-up 1-down */
michael@0: #define SCAN_DWELL	0x70
michael@0: #define SRCH_ON		0x80
michael@0: 
michael@0: /* RDS CONFIG */
michael@0: #define RDS_CONFIG_PSALL 0x01
michael@0: 
michael@0: #define FM_ENABLE	0x22
michael@0: #define SET_REG_FIELD(reg, val, offset, mask) \
michael@0: 	(reg = (reg & ~mask) | (((val) << offset) & mask))
michael@0: #define GET_REG_FIELD(reg, offset, mask) ((reg & mask) >> offset)
michael@0: #define RSH_DATA(val, offset)    ((val) >> (offset))
michael@0: #define LSH_DATA(val, offset)    ((val) << (offset))
michael@0: #define GET_ABS_VAL(val)        ((val) & (0xFF))
michael@0: 
michael@0: enum radio_state_t {
michael@0: 	FM_OFF,
michael@0: 	FM_RECV,
michael@0: 	FM_TRANS,
michael@0: 	FM_RESET,
michael@0: };
michael@0: 
michael@0: #define XFRCTRL_WRITE   (1 << 7)
michael@0: 
michael@0: /* Interrupt status */
michael@0: 
michael@0: /* interrupt register 1 */
michael@0: #define	READY		(1 << 0) /* Radio ready after powerup or reset */
michael@0: #define	TUNE		(1 << 1) /* Tune completed */
michael@0: #define	SEARCH		(1 << 2) /* Search completed (read FREQ) */
michael@0: #define	SCANNEXT	(1 << 3) /* Scanning for next station */
michael@0: #define	SIGNAL		(1 << 4) /* Signal indicator change (read SIGSTATE) */
michael@0: #define	INTF		(1 << 5) /* Interference cnt has fallen outside range */
michael@0: #define	SYNC		(1 << 6) /* RDS sync state change (read RDSSYNC) */
michael@0: #define	AUDIO		(1 << 7) /* Audio Control indicator (read AUDIOIND) */
michael@0: 
michael@0: /* interrupt register 2 */
michael@0: #define	RDSDAT		(1 << 0) /* New unread RDS data group available */
michael@0: #define	BLOCKB		(1 << 1) /* Block-B match condition exists */
michael@0: #define	PROGID		(1 << 2) /* Block-A or Block-C matched stored PI value*/
michael@0: #define	RDSPS		(1 << 3) /* New RDS Program Service Table available */
michael@0: #define	RDSRT		(1 << 4) /* New RDS Radio Text available */
michael@0: #define	RDSAF		(1 << 5) /* New RDS AF List available */
michael@0: #define	TXRDSDAT	(1 << 6) /* Transmitted an RDS group */
michael@0: #define	TXRDSDONE	(1 << 7) /* RDS raw group one-shot transmit completed */
michael@0: 
michael@0: /* interrupt register 3 */
michael@0: #define	TRANSFER	(1 << 0) /* Data transfer (XFR) completed */
michael@0: #define	RDSPROC		(1 << 1) /* Dynamic RDS Processing complete */
michael@0: #define	ERROR		(1 << 7) /* Err occurred.Read code to determine cause */
michael@0: 
michael@0: 
michael@0: #define	FM_TX_PWR_LVL_0		0 /* Lowest power lvl that can be set for Tx */
michael@0: #define	FM_TX_PWR_LVL_MAX	7 /* Max power lvl for Tx */
michael@0: /* Transfer */
michael@0: enum tavarua_xfr_ctrl_t {
michael@0: 	RDS_PS_0 = 0x01,
michael@0: 	RDS_PS_1,
michael@0: 	RDS_PS_2,
michael@0: 	RDS_PS_3,
michael@0: 	RDS_PS_4,
michael@0: 	RDS_PS_5,
michael@0: 	RDS_PS_6,
michael@0: 	RDS_RT_0,
michael@0: 	RDS_RT_1,
michael@0: 	RDS_RT_2,
michael@0: 	RDS_RT_3,
michael@0: 	RDS_RT_4,
michael@0: 	RDS_AF_0,
michael@0: 	RDS_AF_1,
michael@0: 	RDS_CONFIG,
michael@0: 	RDS_TX_GROUPS,
michael@0: 	RDS_COUNT_0,
michael@0: 	RDS_COUNT_1,
michael@0: 	RDS_COUNT_2,
michael@0: 	RADIO_CONFIG,
michael@0: 	RX_CONFIG,
michael@0: 	RX_TIMERS,
michael@0: 	RX_STATIONS_0,
michael@0: 	RX_STATIONS_1,
michael@0: 	INT_CTRL,
michael@0: 	ERROR_CODE,
michael@0: 	CHIPID,
michael@0: 	CAL_DAT_0 = 0x20,
michael@0: 	CAL_DAT_1,
michael@0: 	CAL_DAT_2,
michael@0: 	CAL_DAT_3,
michael@0: 	CAL_CFG_0,
michael@0: 	CAL_CFG_1,
michael@0: 	DIG_INTF_0,
michael@0: 	DIG_INTF_1,
michael@0: 	DIG_AGC_0,
michael@0: 	DIG_AGC_1,
michael@0: 	DIG_AGC_2,
michael@0: 	DIG_AUDIO_0,
michael@0: 	DIG_AUDIO_1,
michael@0: 	DIG_AUDIO_2,
michael@0: 	DIG_AUDIO_3,
michael@0: 	DIG_AUDIO_4,
michael@0: 	DIG_RXRDS,
michael@0: 	DIG_DCC,
michael@0: 	DIG_SPUR,
michael@0: 	DIG_MPXDCC,
michael@0: 	DIG_PILOT,
michael@0: 	DIG_DEMOD,
michael@0: 	DIG_MOST,
michael@0: 	DIG_TX_0,
michael@0: 	DIG_TX_1,
michael@0: 	PHY_TXGAIN = 0x3B,
michael@0: 	PHY_CONFIG,
michael@0: 	PHY_TXBLOCK,
michael@0: 	PHY_TCB,
michael@0: 	XFR_PEEK_MODE = 0x40,
michael@0: 	XFR_POKE_MODE = 0xC0,
michael@0: 	TAVARUA_XFR_CTRL_MAX
michael@0: };
michael@0: 
michael@0: enum tavarua_evt_t {
michael@0: 	TAVARUA_EVT_RADIO_READY,
michael@0: 	TAVARUA_EVT_TUNE_SUCC,
michael@0: 	TAVARUA_EVT_SEEK_COMPLETE,
michael@0: 	TAVARUA_EVT_SCAN_NEXT,
michael@0: 	TAVARUA_EVT_NEW_RAW_RDS,
michael@0: 	TAVARUA_EVT_NEW_RT_RDS,
michael@0: 	TAVARUA_EVT_NEW_PS_RDS,
michael@0: 	TAVARUA_EVT_ERROR,
michael@0: 	TAVARUA_EVT_BELOW_TH,
michael@0: 	TAVARUA_EVT_ABOVE_TH,
michael@0: 	TAVARUA_EVT_STEREO,
michael@0: 	TAVARUA_EVT_MONO,
michael@0: 	TAVARUA_EVT_RDS_AVAIL,
michael@0: 	TAVARUA_EVT_RDS_NOT_AVAIL,
michael@0: 	TAVARUA_EVT_NEW_SRCH_LIST,
michael@0: 	TAVARUA_EVT_NEW_AF_LIST,
michael@0: 	TAVARUA_EVT_TXRDSDAT,
michael@0: 	TAVARUA_EVT_TXRDSDONE,
michael@0: 	TAVARUA_EVT_RADIO_DISABLED
michael@0: };
michael@0: 
michael@0: enum tavarua_region_t {
michael@0: 	TAVARUA_REGION_US,
michael@0: 	TAVARUA_REGION_EU,
michael@0: 	TAVARUA_REGION_JAPAN,
michael@0: 	TAVARUA_REGION_JAPAN_WIDE,
michael@0: 	TAVARUA_REGION_OTHER
michael@0: };
michael@0: 
michael@0: #endif /* __LINUX_TAVARUA_H */