michael@0: // Copyright 2013 Google Inc. All Rights Reserved.
michael@0: //
michael@0: // Licensed under the Apache License, Version 2.0 (the "License");
michael@0: // you may not use this file except in compliance with the License.
michael@0: // You may obtain a copy of the License at
michael@0: //
michael@0: //     http://www.apache.org/licenses/LICENSE-2.0
michael@0: //
michael@0: // Unless required by applicable law or agreed to in writing, software
michael@0: // distributed under the License is distributed on an "AS IS" BASIS,
michael@0: // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
michael@0: // See the License for the specific language governing permissions and
michael@0: // limitations under the License.
michael@0: 
michael@0: //
michael@0: // These are weird things we need to do to get this compiling on
michael@0: // random systems [subset].
michael@0: 
michael@0: #ifndef BASE_PORT_H_
michael@0: #define BASE_PORT_H_
michael@0: 
michael@0: #include <string.h>         // for memcpy()
michael@0: #include "integral_types.h"
michael@0: 
michael@0: namespace CLD2 {
michael@0: 
michael@0: // Portable handling of unaligned loads, stores, and copies.
michael@0: // On some platforms, like ARM, the copy functions can be more efficient
michael@0: // then a load and a store.
michael@0: 
michael@0: #if defined(ARCH_PIII) || defined(ARCH_ATHLON) || defined(ARCH_K8) || defined(_ARCH_PPC)
michael@0: 
michael@0: // x86 and x86-64 can perform unaligned loads/stores directly;
michael@0: // modern PowerPC hardware can also do unaligned integer loads and stores;
michael@0: // but note: the FPU still sends unaligned loads and stores to a trap handler!
michael@0: 
michael@0: #define UNALIGNED_LOAD16(_p) (*reinterpret_cast<const uint16 *>(_p))
michael@0: #define UNALIGNED_LOAD32(_p) (*reinterpret_cast<const uint32 *>(_p))
michael@0: #define UNALIGNED_LOAD64(_p) (*reinterpret_cast<const uint64 *>(_p))
michael@0: 
michael@0: #define UNALIGNED_STORE16(_p, _val) (*reinterpret_cast<uint16 *>(_p) = (_val))
michael@0: #define UNALIGNED_STORE32(_p, _val) (*reinterpret_cast<uint32 *>(_p) = (_val))
michael@0: #define UNALIGNED_STORE64(_p, _val) (*reinterpret_cast<uint64 *>(_p) = (_val))
michael@0: 
michael@0: #elif defined(__arm__) && \
michael@0:       !defined(__ARM_ARCH_5__) && \
michael@0:       !defined(__ARM_ARCH_5T__) && \
michael@0:       !defined(__ARM_ARCH_5TE__) && \
michael@0:       !defined(__ARM_ARCH_5TEJ__) && \
michael@0:       !defined(__ARM_ARCH_6__) && \
michael@0:       !defined(__ARM_ARCH_6J__) && \
michael@0:       !defined(__ARM_ARCH_6K__) && \
michael@0:       !defined(__ARM_ARCH_6Z__) && \
michael@0:       !defined(__ARM_ARCH_6ZK__) && \
michael@0:       !defined(__ARM_ARCH_6T2__)
michael@0: 
michael@0: // ARMv7 and newer support native unaligned accesses, but only of 16-bit
michael@0: // and 32-bit values (not 64-bit); older versions either raise a fatal signal,
michael@0: // do an unaligned read and rotate the words around a bit, or do the reads very
michael@0: // slowly (trip through kernel mode). There's no simple #define that says just
michael@0: // “ARMv7 or higher”, so we have to filter away all ARMv5 and ARMv6
michael@0: // sub-architectures. Newer gcc (>= 4.6) set an __ARM_FEATURE_ALIGNED #define,
michael@0: // so in time, maybe we can move on to that.
michael@0: //
michael@0: // This is a mess, but there's not much we can do about it.
michael@0: 
michael@0: #define UNALIGNED_LOAD16(_p) (*reinterpret_cast<const uint16 *>(_p))
michael@0: #define UNALIGNED_LOAD32(_p) (*reinterpret_cast<const uint32 *>(_p))
michael@0: 
michael@0: #define UNALIGNED_STORE16(_p, _val) (*reinterpret_cast<uint16 *>(_p) = (_val))
michael@0: #define UNALIGNED_STORE32(_p, _val) (*reinterpret_cast<uint32 *>(_p) = (_val))
michael@0: 
michael@0: // TODO(sesse): NEON supports unaligned 64-bit loads and stores.
michael@0: // See if that would be more efficient on platforms supporting it,
michael@0: // at least for copies.
michael@0: 
michael@0: inline uint64 UNALIGNED_LOAD64(const void *p) {
michael@0:   uint64 t;
michael@0:   memcpy(&t, p, sizeof t);
michael@0:   return t;
michael@0: }
michael@0: 
michael@0: inline void UNALIGNED_STORE64(void *p, uint64 v) {
michael@0:   memcpy(p, &v, sizeof v);
michael@0: }
michael@0: 
michael@0: #else
michael@0: 
michael@0: #define NEED_ALIGNED_LOADS
michael@0: 
michael@0: // These functions are provided for architectures that don't support
michael@0: // unaligned loads and stores.
michael@0: 
michael@0: inline uint16 UNALIGNED_LOAD16(const void *p) {
michael@0:   uint16 t;
michael@0:   memcpy(&t, p, sizeof t);
michael@0:   return t;
michael@0: }
michael@0: 
michael@0: inline uint32 UNALIGNED_LOAD32(const void *p) {
michael@0:   uint32 t;
michael@0:   memcpy(&t, p, sizeof t);
michael@0:   return t;
michael@0: }
michael@0: 
michael@0: inline uint64 UNALIGNED_LOAD64(const void *p) {
michael@0:   uint64 t;
michael@0:   memcpy(&t, p, sizeof t);
michael@0:   return t;
michael@0: }
michael@0: 
michael@0: inline void UNALIGNED_STORE16(void *p, uint16 v) {
michael@0:   memcpy(p, &v, sizeof v);
michael@0: }
michael@0: 
michael@0: inline void UNALIGNED_STORE32(void *p, uint32 v) {
michael@0:   memcpy(p, &v, sizeof v);
michael@0: }
michael@0: 
michael@0: inline void UNALIGNED_STORE64(void *p, uint64 v) {
michael@0:   memcpy(p, &v, sizeof v);
michael@0: }
michael@0: 
michael@0: #endif
michael@0: 
michael@0: }       // End namespace CLD2
michael@0: 
michael@0: #endif  // BASE_PORT_H_