michael@0: ;********************************************************************
michael@0: ;*                                                                  *
michael@0: ;* THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE.   *
michael@0: ;* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS     *
michael@0: ;* GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
michael@0: ;* IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING.       *
michael@0: ;*                                                                  *
michael@0: ;* THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2010                *
michael@0: ;* by the Xiph.Org Foundation and contributors http://www.xiph.org/ *
michael@0: ;*                                                                  *
michael@0: ;********************************************************************
michael@0: ; Original implementation:
michael@0: ;  Copyright (C) 2009 Robin Watts for Pinknoise Productions Ltd
michael@0: ; last mod: $Id: armfrag.s 17481 2010-10-03 22:49:42Z tterribe $
michael@0: ;********************************************************************
michael@0: 
michael@0: 	AREA	|.text|, CODE, READONLY
michael@0: 
michael@0: 	; Explicitly specifying alignment here because some versions of
michael@0: 	; gas don't align code correctly. See
michael@0: 	; http://lists.gnu.org/archive/html/bug-binutils/2011-06/msg00199.html
michael@0: 	; https://bugzilla.mozilla.org/show_bug.cgi?id=920992
michael@0: 	ALIGN
michael@0: 
michael@0: 	GET	armopts.s
michael@0: 
michael@0: ; Vanilla ARM v4 versions
michael@0: 	EXPORT	oc_frag_copy_list_arm
michael@0: 	EXPORT	oc_frag_recon_intra_arm
michael@0: 	EXPORT	oc_frag_recon_inter_arm
michael@0: 	EXPORT	oc_frag_recon_inter2_arm
michael@0: 
michael@0: oc_frag_copy_list_arm PROC
michael@0: 	; r0 = _dst_frame
michael@0: 	; r1 = _src_frame
michael@0: 	; r2 = _ystride
michael@0: 	; r3 = _fragis
michael@0: 	; <> = _nfragis
michael@0: 	; <> = _frag_buf_offs
michael@0: 	LDR	r12,[r13]		; r12 = _nfragis
michael@0: 	STMFD	r13!,{r4-r6,r11,r14}
michael@0: 	SUBS	r12, r12, #1
michael@0: 	LDR	r4,[r3],#4		; r4 = _fragis[fragii]
michael@0: 	LDRGE	r14,[r13,#4*6]		; r14 = _frag_buf_offs
michael@0: 	BLT	ofcl_arm_end
michael@0: 	SUB	r2, r2, #4
michael@0: ofcl_arm_lp
michael@0: 	LDR	r11,[r14,r4,LSL #2]	; r11 = _frag_buf_offs[_fragis[fragii]]
michael@0: 	SUBS	r12, r12, #1
michael@0: 	; Stall (on XScale)
michael@0: 	ADD	r4, r1, r11		; r4 = _src_frame+frag_buf_off
michael@0: 	LDR	r6, [r4], #4
michael@0: 	ADD	r11,r0, r11		; r11 = _dst_frame+frag_buf_off
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4], r2
michael@0: 	STR	r6, [r11],#4
michael@0: 	LDR	r6, [r4], #4
michael@0: 	STR	r5, [r11],r2
michael@0: 	LDR	r5, [r4]
michael@0: 	LDRGE	r4,[r3],#4		; r4 = _fragis[fragii]
michael@0: 	STR	r6, [r11],#4
michael@0: 	STR	r5, [r11]
michael@0: 	BGE	ofcl_arm_lp
michael@0: ofcl_arm_end
michael@0: 	LDMFD	r13!,{r4-r6,r11,PC}
michael@0: oc_frag_recon_intra_arm
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 =       int            _ystride
michael@0: 	; r2 = const ogg_int16_t    _residue[64]
michael@0: 	STMFD	r13!,{r4,r5,r14}
michael@0: 	MOV	r14,#8
michael@0: 	MOV	r5, #255
michael@0: 	SUB	r1, r1, #7
michael@0: ofrintra_lp_arm
michael@0: 	LDRSH	r3, [r2], #2
michael@0: 	LDRSH	r4, [r2], #2
michael@0: 	LDRSH	r12,[r2], #2
michael@0: 	ADDS	r3, r3, #128
michael@0: 	CMPGT	r5, r3
michael@0: 	EORLT	r3, r5, r3, ASR #32
michael@0: 	STRB	r3, [r0], #1
michael@0: 	ADDS	r4, r4, #128
michael@0: 	CMPGT	r5, r4
michael@0: 	EORLT	r4, r5, r4, ASR #32
michael@0: 	LDRSH	r3, [r2], #2
michael@0: 	STRB	r4, [r0], #1
michael@0: 	ADDS	r12,r12,#128
michael@0: 	CMPGT	r5, r12
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	LDRSH	r4, [r2], #2
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r3, r3, #128
michael@0: 	CMPGT	r5, r3
michael@0: 	EORLT	r3, r5, r3, ASR #32
michael@0: 	LDRSH	r12,[r2], #2
michael@0: 	STRB	r3, [r0], #1
michael@0: 	ADDS	r4, r4, #128
michael@0: 	CMPGT	r5, r4
michael@0: 	EORLT	r4, r5, r4, ASR #32
michael@0: 	LDRSH	r3, [r2], #2
michael@0: 	STRB	r4, [r0], #1
michael@0: 	ADDS	r12,r12,#128
michael@0: 	CMPGT	r5, r12
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	LDRSH	r4, [r2], #2
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r3, r3, #128
michael@0: 	CMPGT	r5, r3
michael@0: 	EORLT	r3, r5, r3, ASR #32
michael@0: 	STRB	r3, [r0], #1
michael@0: 	ADDS	r4, r4, #128
michael@0: 	CMPGT	r5, r4
michael@0: 	EORLT	r4, r5, r4, ASR #32
michael@0: 	STRB	r4, [r0], r1
michael@0: 	SUBS	r14,r14,#1
michael@0: 	BGT	ofrintra_lp_arm
michael@0: 	LDMFD	r13!,{r4,r5,PC}
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter_arm PROC
michael@0: 	; r0 =       unsigned char *dst
michael@0: 	; r1 = const unsigned char *src
michael@0: 	; r2 =       int            ystride
michael@0: 	; r3 = const ogg_int16_t    residue[64]
michael@0: 	STMFD	r13!,{r5,r9-r11,r14}
michael@0: 	MOV	r9, #8
michael@0: 	MOV	r5, #255
michael@0: 	SUB	r2, r2, #7
michael@0: ofrinter_lp_arm
michael@0: 	LDRSH	r12,[r3], #2
michael@0: 	LDRB	r14,[r1], #1
michael@0: 	LDRSH	r11,[r3], #2
michael@0: 	LDRB	r10,[r1], #1
michael@0: 	ADDS	r12,r12,r14
michael@0: 	CMPGT	r5, r12
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r11,r11,r10
michael@0: 	CMPGT	r5, r11
michael@0: 	LDRSH	r12,[r3], #2
michael@0: 	LDRB	r14,[r1], #1
michael@0: 	EORLT	r11,r5, r11,ASR #32
michael@0: 	STRB	r11,[r0], #1
michael@0: 	ADDS	r12,r12,r14
michael@0: 	CMPGT	r5, r12
michael@0: 	LDRSH	r11,[r3], #2
michael@0: 	LDRB	r10,[r1], #1
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r11,r11,r10
michael@0: 	CMPGT	r5, r11
michael@0: 	LDRSH	r12,[r3], #2
michael@0: 	LDRB	r14,[r1], #1
michael@0: 	EORLT	r11,r5, r11,ASR #32
michael@0: 	STRB	r11,[r0], #1
michael@0: 	ADDS	r12,r12,r14
michael@0: 	CMPGT	r5, r12
michael@0: 	LDRSH	r11,[r3], #2
michael@0: 	LDRB	r10,[r1], #1
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r11,r11,r10
michael@0: 	CMPGT	r5, r11
michael@0: 	LDRSH	r12,[r3], #2
michael@0: 	LDRB	r14,[r1], #1
michael@0: 	EORLT	r11,r5, r11,ASR #32
michael@0: 	STRB	r11,[r0], #1
michael@0: 	ADDS	r12,r12,r14
michael@0: 	CMPGT	r5, r12
michael@0: 	LDRSH	r11,[r3], #2
michael@0: 	LDRB	r10,[r1], r2
michael@0: 	EORLT	r12,r5, r12,ASR #32
michael@0: 	STRB	r12,[r0], #1
michael@0: 	ADDS	r11,r11,r10
michael@0: 	CMPGT	r5, r11
michael@0: 	EORLT	r11,r5, r11,ASR #32
michael@0: 	STRB	r11,[r0], r2
michael@0: 	SUBS	r9, r9, #1
michael@0: 	BGT	ofrinter_lp_arm
michael@0: 	LDMFD	r13!,{r5,r9-r11,PC}
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter2_arm PROC
michael@0: 	; r0 =       unsigned char *dst
michael@0: 	; r1 = const unsigned char *src1
michael@0: 	; r2 = const unsigned char *src2
michael@0: 	; r3 =       int            ystride
michael@0: 	LDR	r12,[r13]
michael@0: 	; r12= const ogg_int16_t    residue[64]
michael@0: 	STMFD	r13!,{r4-r8,r14}
michael@0: 	MOV	r14,#8
michael@0: 	MOV	r8, #255
michael@0: 	SUB	r3, r3, #7
michael@0: ofrinter2_lp_arm
michael@0: 	LDRB	r5, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	LDRB	r7, [r1], #1
michael@0: 	ADD	r5, r5, r6
michael@0: 	ADDS	r5, r4, r5, LSR #1
michael@0: 	CMPGT	r8, r5
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r5, r8, r5, ASR #32
michael@0: 	STRB	r5, [r0], #1
michael@0: 	ADD	r7, r7, r6
michael@0: 	ADDS	r7, r4, r7, LSR #1
michael@0: 	CMPGT	r8, r7
michael@0: 	LDRB	r5, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r7, r8, r7, ASR #32
michael@0: 	STRB	r7, [r0], #1
michael@0: 	ADD	r5, r5, r6
michael@0: 	ADDS	r5, r4, r5, LSR #1
michael@0: 	CMPGT	r8, r5
michael@0: 	LDRB	r7, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r5, r8, r5, ASR #32
michael@0: 	STRB	r5, [r0], #1
michael@0: 	ADD	r7, r7, r6
michael@0: 	ADDS	r7, r4, r7, LSR #1
michael@0: 	CMPGT	r8, r7
michael@0: 	LDRB	r5, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r7, r8, r7, ASR #32
michael@0: 	STRB	r7, [r0], #1
michael@0: 	ADD	r5, r5, r6
michael@0: 	ADDS	r5, r4, r5, LSR #1
michael@0: 	CMPGT	r8, r5
michael@0: 	LDRB	r7, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r5, r8, r5, ASR #32
michael@0: 	STRB	r5, [r0], #1
michael@0: 	ADD	r7, r7, r6
michael@0: 	ADDS	r7, r4, r7, LSR #1
michael@0: 	CMPGT	r8, r7
michael@0: 	LDRB	r5, [r1], #1
michael@0: 	LDRB	r6, [r2], #1
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r7, r8, r7, ASR #32
michael@0: 	STRB	r7, [r0], #1
michael@0: 	ADD	r5, r5, r6
michael@0: 	ADDS	r5, r4, r5, LSR #1
michael@0: 	CMPGT	r8, r5
michael@0: 	LDRB	r7, [r1], r3
michael@0: 	LDRB	r6, [r2], r3
michael@0: 	LDRSH	r4, [r12],#2
michael@0: 	EORLT	r5, r8, r5, ASR #32
michael@0: 	STRB	r5, [r0], #1
michael@0: 	ADD	r7, r7, r6
michael@0: 	ADDS	r7, r4, r7, LSR #1
michael@0: 	CMPGT	r8, r7
michael@0: 	EORLT	r7, r8, r7, ASR #32
michael@0: 	STRB	r7, [r0], r3
michael@0: 	SUBS	r14,r14,#1
michael@0: 	BGT	ofrinter2_lp_arm
michael@0: 	LDMFD	r13!,{r4-r8,PC}
michael@0: 	ENDP
michael@0: 
michael@0:  [ OC_ARM_ASM_EDSP
michael@0: 	EXPORT	oc_frag_copy_list_edsp
michael@0: 
michael@0: oc_frag_copy_list_edsp PROC
michael@0: 	; r0 = _dst_frame
michael@0: 	; r1 = _src_frame
michael@0: 	; r2 = _ystride
michael@0: 	; r3 = _fragis
michael@0: 	; <> = _nfragis
michael@0: 	; <> = _frag_buf_offs
michael@0: 	LDR	r12,[r13]		; r12 = _nfragis
michael@0: 	STMFD	r13!,{r4-r11,r14}
michael@0: 	SUBS	r12, r12, #1
michael@0: 	LDRGE	r5, [r3],#4		; r5 = _fragis[fragii]
michael@0: 	LDRGE	r14,[r13,#4*10]		; r14 = _frag_buf_offs
michael@0: 	BLT	ofcl_edsp_end
michael@0: ofcl_edsp_lp
michael@0: 	MOV	r4, r1
michael@0: 	LDR	r5, [r14,r5, LSL #2]	; r5 = _frag_buf_offs[_fragis[fragii]]
michael@0: 	SUBS	r12, r12, #1
michael@0: 	; Stall (on XScale)
michael@0: 	LDRD	r6, [r4, r5]!		; r4 = _src_frame+frag_buf_off
michael@0: 	LDRD	r8, [r4, r2]!
michael@0: 	; Stall
michael@0: 	STRD	r6, [r5, r0]!		; r5 = _dst_frame+frag_buf_off
michael@0: 	STRD	r8, [r5, r2]!
michael@0: 	; Stall
michael@0: 	LDRD	r6, [r4, r2]!	; On Xscale at least, doing 3 consecutive
michael@0: 	LDRD	r8, [r4, r2]!	; loads causes a stall, but that's no worse
michael@0: 	LDRD	r10,[r4, r2]!	; than us only doing 2, and having to do
michael@0: 				; another pair of LDRD/STRD later on.
michael@0: 	; Stall
michael@0: 	STRD	r6, [r5, r2]!
michael@0: 	STRD	r8, [r5, r2]!
michael@0: 	STRD	r10,[r5, r2]!
michael@0: 	LDRD	r6, [r4, r2]!
michael@0: 	LDRD	r8, [r4, r2]!
michael@0: 	LDRD	r10,[r4, r2]!
michael@0: 	STRD	r6, [r5, r2]!
michael@0: 	STRD	r8, [r5, r2]!
michael@0: 	STRD	r10,[r5, r2]!
michael@0: 	LDRGE	r5, [r3],#4		; r5 = _fragis[fragii]
michael@0: 	BGE	ofcl_edsp_lp
michael@0: ofcl_edsp_end
michael@0: 	LDMFD	r13!,{r4-r11,PC}
michael@0: 	ENDP
michael@0:  ]
michael@0: 
michael@0:  [ OC_ARM_ASM_MEDIA
michael@0: 	EXPORT	oc_frag_recon_intra_v6
michael@0: 	EXPORT	oc_frag_recon_inter_v6
michael@0: 	EXPORT	oc_frag_recon_inter2_v6
michael@0: 
michael@0: oc_frag_recon_intra_v6 PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 =       int            _ystride
michael@0: 	; r2 = const ogg_int16_t    _residue[64]
michael@0: 	STMFD	r13!,{r4-r6,r14}
michael@0: 	MOV	r14,#8
michael@0: 	MOV	r12,r2
michael@0: 	LDR	r6, =0x00800080
michael@0: ofrintra_v6_lp
michael@0: 	LDRD	r2, [r12],#8	; r2 = 11110000 r3 = 33332222
michael@0: 	LDRD	r4, [r12],#8	; r4 = 55554444 r5 = 77776666
michael@0: 	SUBS	r14,r14,#1
michael@0: 	QADD16	r2, r2, r6
michael@0: 	QADD16	r3, r3, r6
michael@0: 	QADD16	r4, r4, r6
michael@0: 	QADD16	r5, r5, r6
michael@0: 	USAT16	r2, #8, r2		; r2 = __11__00
michael@0: 	USAT16	r3, #8, r3		; r3 = __33__22
michael@0: 	USAT16	r4, #8, r4		; r4 = __55__44
michael@0: 	USAT16	r5, #8, r5		; r5 = __77__66
michael@0: 	ORR	r2, r2, r2, LSR #8	; r2 = __111100
michael@0: 	ORR	r3, r3, r3, LSR #8	; r3 = __333322
michael@0: 	ORR	r4, r4, r4, LSR #8	; r4 = __555544
michael@0: 	ORR	r5, r5, r5, LSR #8	; r5 = __777766
michael@0: 	PKHBT   r2, r2, r3, LSL #16     ; r2 = 33221100
michael@0: 	PKHBT   r3, r4, r5, LSL #16     ; r3 = 77665544
michael@0: 	STRD	r2, [r0], r1
michael@0: 	BGT	ofrintra_v6_lp
michael@0: 	LDMFD	r13!,{r4-r6,PC}
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter_v6 PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 = const unsigned char *_src
michael@0: 	; r2 =       int            _ystride
michael@0: 	; r3 = const ogg_int16_t    _residue[64]
michael@0: 	STMFD	r13!,{r4-r7,r14}
michael@0: 	MOV	r14,#8
michael@0: ofrinter_v6_lp
michael@0: 	LDRD	r6, [r3], #8		; r6 = 11110000 r7 = 33332222
michael@0: 	SUBS	r14,r14,#1
michael@0:  [ OC_ARM_CAN_UNALIGN_LDRD
michael@0: 	LDRD	r4, [r1], r2	; Unaligned ; r4 = 33221100 r5 = 77665544
michael@0:  |
michael@0: 	LDR	r5, [r1, #4]
michael@0: 	LDR	r4, [r1], r2
michael@0:  ]
michael@0: 	PKHBT	r12,r6, r7, LSL #16	; r12= 22220000
michael@0: 	PKHTB	r7, r7, r6, ASR #16	; r7 = 33331111
michael@0: 	UXTB16	r6,r4			; r6 = __22__00
michael@0: 	UXTB16	r4,r4, ROR #8		; r4 = __33__11
michael@0: 	QADD16	r12,r12,r6		; r12= xx22xx00
michael@0: 	QADD16	r4, r7, r4		; r4 = xx33xx11
michael@0: 	LDRD	r6, [r3], #8		; r6 = 55554444 r7 = 77776666
michael@0: 	USAT16	r4, #8, r4		; r4 = __33__11
michael@0: 	USAT16	r12,#8,r12		; r12= __22__00
michael@0: 	ORR	r4, r12,r4, LSL #8	; r4 = 33221100
michael@0: 	PKHBT	r12,r6, r7, LSL #16	; r12= 66664444
michael@0: 	PKHTB	r7, r7, r6, ASR #16	; r7 = 77775555
michael@0: 	UXTB16	r6,r5			; r6 = __66__44
michael@0: 	UXTB16	r5,r5, ROR #8		; r5 = __77__55
michael@0: 	QADD16	r12,r12,r6		; r12= xx66xx44
michael@0: 	QADD16	r5, r7, r5		; r5 = xx77xx55
michael@0: 	USAT16	r12,#8, r12		; r12= __66__44
michael@0: 	USAT16	r5, #8, r5		; r4 = __77__55
michael@0: 	ORR	r5, r12,r5, LSL #8	; r5 = 33221100
michael@0: 	STRD	r4, [r0], r2
michael@0: 	BGT	ofrinter_v6_lp
michael@0: 	LDMFD	r13!,{r4-r7,PC}
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter2_v6 PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 = const unsigned char *_src1
michael@0: 	; r2 = const unsigned char *_src2
michael@0: 	; r3 =       int            _ystride
michael@0: 	LDR	r12,[r13]
michael@0: 	; r12= const ogg_int16_t    _residue[64]
michael@0: 	STMFD	r13!,{r4-r9,r14}
michael@0: 	MOV	r14,#8
michael@0: ofrinter2_v6_lp
michael@0: 	LDRD	r6, [r12,#8]	; r6 = 55554444 r7 = 77776666
michael@0: 	SUBS	r14,r14,#1
michael@0: 	LDR	r4, [r1, #4]	; Unaligned	; r4 = src1[1] = 77665544
michael@0: 	LDR	r5, [r2, #4]	; Unaligned	; r5 = src2[1] = 77665544
michael@0: 	PKHBT	r8, r6, r7, LSL #16	; r8 = 66664444
michael@0: 	PKHTB	r9, r7, r6, ASR #16	; r9 = 77775555
michael@0: 	UHADD8	r4, r4, r5	; r4 = (src1[7,6,5,4] + src2[7,6,5,4])>>1
michael@0: 	UXTB16	r5, r4			; r5 = __66__44
michael@0: 	UXTB16	r4, r4, ROR #8		; r4 = __77__55
michael@0: 	QADD16	r8, r8, r5		; r8 = xx66xx44
michael@0: 	QADD16	r9, r9, r4		; r9 = xx77xx55
michael@0: 	LDRD	r6,[r12],#16	; r6 = 33332222 r7 = 11110000
michael@0: 	USAT16	r8, #8, r8		; r8 = __66__44
michael@0: 	LDR	r4, [r1], r3	; Unaligned	; r4 = src1[0] = 33221100
michael@0: 	USAT16	r9, #8, r9		; r9 = __77__55
michael@0: 	LDR	r5, [r2], r3	; Unaligned	; r5 = src2[0] = 33221100
michael@0: 	ORR	r9, r8, r9, LSL #8	; r9 = 77665544
michael@0: 	PKHBT	r8, r6, r7, LSL #16	; r8 = 22220000
michael@0: 	UHADD8	r4, r4, r5	; r4 = (src1[3,2,1,0] + src2[3,2,1,0])>>1
michael@0: 	PKHTB	r7, r7, r6, ASR #16	; r7 = 33331111
michael@0: 	UXTB16	r5, r4			; r5 = __22__00
michael@0: 	UXTB16	r4, r4, ROR #8		; r4 = __33__11
michael@0: 	QADD16	r8, r8, r5		; r8 = xx22xx00
michael@0: 	QADD16	r7, r7, r4		; r7 = xx33xx11
michael@0: 	USAT16	r8, #8, r8		; r8 = __22__00
michael@0: 	USAT16	r7, #8, r7		; r7 = __33__11
michael@0: 	ORR	r8, r8, r7, LSL #8	; r8 = 33221100
michael@0: 	STRD	r8, [r0], r3
michael@0: 	BGT	ofrinter2_v6_lp
michael@0: 	LDMFD	r13!,{r4-r9,PC}
michael@0: 	ENDP
michael@0:  ]
michael@0: 
michael@0:  [ OC_ARM_ASM_NEON
michael@0: 	EXPORT	oc_frag_copy_list_neon
michael@0: 	EXPORT	oc_frag_recon_intra_neon
michael@0: 	EXPORT	oc_frag_recon_inter_neon
michael@0: 	EXPORT	oc_frag_recon_inter2_neon
michael@0: 
michael@0: oc_frag_copy_list_neon PROC
michael@0: 	; r0 = _dst_frame
michael@0: 	; r1 = _src_frame
michael@0: 	; r2 = _ystride
michael@0: 	; r3 = _fragis
michael@0: 	; <> = _nfragis
michael@0: 	; <> = _frag_buf_offs
michael@0: 	LDR	r12,[r13]		; r12 = _nfragis
michael@0: 	STMFD	r13!,{r4-r7,r14}
michael@0: 	CMP	r12, #1
michael@0: 	LDRGE	r6, [r3]		; r6 = _fragis[fragii]
michael@0: 	LDRGE	r14,[r13,#4*6]		; r14 = _frag_buf_offs
michael@0: 	BLT	ofcl_neon_end
michael@0: 	; Stall (2 on Xscale)
michael@0: 	LDR	r6, [r14,r6, LSL #2]	; r6 = _frag_buf_offs[_fragis[fragii]]
michael@0: 	; Stall (on XScale)
michael@0: 	MOV	r7, r6			; Guarantee PLD points somewhere valid.
michael@0: ofcl_neon_lp
michael@0: 	ADD	r4, r1, r6
michael@0: 	VLD1.64	{D0}, [r4@64], r2
michael@0: 	ADD	r5, r0, r6
michael@0: 	VLD1.64	{D1}, [r4@64], r2
michael@0: 	SUBS	r12, r12, #1
michael@0: 	VLD1.64	{D2}, [r4@64], r2
michael@0: 	LDRGT	r6, [r3,#4]!		; r6 = _fragis[fragii]
michael@0: 	VLD1.64	{D3}, [r4@64], r2
michael@0: 	LDRGT	r6, [r14,r6, LSL #2]	; r6 = _frag_buf_offs[_fragis[fragii]]
michael@0: 	VLD1.64	{D4}, [r4@64], r2
michael@0: 	ADDGT	r7, r1, r6
michael@0: 	VLD1.64	{D5}, [r4@64], r2
michael@0: 	PLD	[r7]
michael@0: 	VLD1.64	{D6}, [r4@64], r2
michael@0: 	PLD	[r7, r2]
michael@0: 	VLD1.64	{D7}, [r4@64]
michael@0: 	PLD	[r7, r2, LSL #1]
michael@0: 	VST1.64	{D0}, [r5@64], r2
michael@0: 	ADDGT	r7, r7, r2, LSL #2
michael@0: 	VST1.64	{D1}, [r5@64], r2
michael@0: 	PLD	[r7, -r2]
michael@0: 	VST1.64	{D2}, [r5@64], r2
michael@0: 	PLD	[r7]
michael@0: 	VST1.64	{D3}, [r5@64], r2
michael@0: 	PLD	[r7, r2]
michael@0: 	VST1.64	{D4}, [r5@64], r2
michael@0: 	PLD	[r7, r2, LSL #1]
michael@0: 	VST1.64	{D5}, [r5@64], r2
michael@0: 	ADDGT	r7, r7, r2, LSL #2
michael@0: 	VST1.64	{D6}, [r5@64], r2
michael@0: 	PLD	[r7, -r2]
michael@0: 	VST1.64	{D7}, [r5@64]
michael@0: 	BGT	ofcl_neon_lp
michael@0: ofcl_neon_end
michael@0: 	LDMFD	r13!,{r4-r7,PC}
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_intra_neon PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 =       int            _ystride
michael@0: 	; r2 = const ogg_int16_t    _residue[64]
michael@0: 	MOV	r3, #128
michael@0: 	VDUP.S16	Q0, r3
michael@0: 	VLDMIA	r2,  {D16-D31}	; D16= 3333222211110000 etc	; 9(8) cycles
michael@0: 	VQADD.S16	Q8, Q8, Q0
michael@0: 	VQADD.S16	Q9, Q9, Q0
michael@0: 	VQADD.S16	Q10,Q10,Q0
michael@0: 	VQADD.S16	Q11,Q11,Q0
michael@0: 	VQADD.S16	Q12,Q12,Q0
michael@0: 	VQADD.S16	Q13,Q13,Q0
michael@0: 	VQADD.S16	Q14,Q14,Q0
michael@0: 	VQADD.S16	Q15,Q15,Q0
michael@0: 	VQMOVUN.S16	D16,Q8	; D16= 7766554433221100		; 1 cycle
michael@0: 	VQMOVUN.S16	D17,Q9	; D17= FFEEDDCCBBAA9988		; 1 cycle
michael@0: 	VQMOVUN.S16	D18,Q10	; D18= NNMMLLKKJJIIHHGG		; 1 cycle
michael@0: 	VST1.64	{D16},[r0@64], r1
michael@0: 	VQMOVUN.S16	D19,Q11	; D19= VVUUTTSSRRQQPPOO		; 1 cycle
michael@0: 	VST1.64	{D17},[r0@64], r1
michael@0: 	VQMOVUN.S16	D20,Q12	; D20= ddccbbaaZZYYXXWW		; 1 cycle
michael@0: 	VST1.64	{D18},[r0@64], r1
michael@0: 	VQMOVUN.S16	D21,Q13	; D21= llkkjjiihhggffee		; 1 cycle
michael@0: 	VST1.64	{D19},[r0@64], r1
michael@0: 	VQMOVUN.S16	D22,Q14	; D22= ttssrrqqppoonnmm		; 1 cycle
michael@0: 	VST1.64	{D20},[r0@64], r1
michael@0: 	VQMOVUN.S16	D23,Q15	; D23= !!@@zzyyxxwwvvuu		; 1 cycle
michael@0: 	VST1.64	{D21},[r0@64], r1
michael@0: 	VST1.64	{D22},[r0@64], r1
michael@0: 	VST1.64	{D23},[r0@64], r1
michael@0: 	MOV	PC,R14
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter_neon PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 = const unsigned char *_src
michael@0: 	; r2 =       int            _ystride
michael@0: 	; r3 = const ogg_int16_t    _residue[64]
michael@0: 	VLDMIA	r3, {D16-D31}	; D16= 3333222211110000 etc	; 9(8) cycles
michael@0: 	VLD1.64	{D0}, [r1], r2
michael@0: 	VLD1.64	{D2}, [r1], r2
michael@0: 	VMOVL.U8	Q0, D0	; Q0 = __77__66__55__44__33__22__11__00
michael@0: 	VLD1.64	{D4}, [r1], r2
michael@0: 	VMOVL.U8	Q1, D2	; etc
michael@0: 	VLD1.64	{D6}, [r1], r2
michael@0: 	VMOVL.U8	Q2, D4
michael@0: 	VMOVL.U8	Q3, D6
michael@0: 	VQADD.S16	Q8, Q8, Q0
michael@0: 	VLD1.64	{D0}, [r1], r2
michael@0: 	VQADD.S16	Q9, Q9, Q1
michael@0: 	VLD1.64	{D2}, [r1], r2
michael@0: 	VQADD.S16	Q10,Q10,Q2
michael@0: 	VLD1.64	{D4}, [r1], r2
michael@0: 	VQADD.S16	Q11,Q11,Q3
michael@0: 	VLD1.64	{D6}, [r1], r2
michael@0: 	VMOVL.U8	Q0, D0
michael@0: 	VMOVL.U8	Q1, D2
michael@0: 	VMOVL.U8	Q2, D4
michael@0: 	VMOVL.U8	Q3, D6
michael@0: 	VQADD.S16	Q12,Q12,Q0
michael@0: 	VQADD.S16	Q13,Q13,Q1
michael@0: 	VQADD.S16	Q14,Q14,Q2
michael@0: 	VQADD.S16	Q15,Q15,Q3
michael@0: 	VQMOVUN.S16	D16,Q8
michael@0: 	VQMOVUN.S16	D17,Q9
michael@0: 	VQMOVUN.S16	D18,Q10
michael@0: 	VST1.64	{D16},[r0@64], r2
michael@0: 	VQMOVUN.S16	D19,Q11
michael@0: 	VST1.64	{D17},[r0@64], r2
michael@0: 	VQMOVUN.S16	D20,Q12
michael@0: 	VST1.64	{D18},[r0@64], r2
michael@0: 	VQMOVUN.S16	D21,Q13
michael@0: 	VST1.64	{D19},[r0@64], r2
michael@0: 	VQMOVUN.S16	D22,Q14
michael@0: 	VST1.64	{D20},[r0@64], r2
michael@0: 	VQMOVUN.S16	D23,Q15
michael@0: 	VST1.64	{D21},[r0@64], r2
michael@0: 	VST1.64	{D22},[r0@64], r2
michael@0: 	VST1.64	{D23},[r0@64], r2
michael@0: 	MOV	PC,R14
michael@0: 	ENDP
michael@0: 
michael@0: oc_frag_recon_inter2_neon PROC
michael@0: 	; r0 =       unsigned char *_dst
michael@0: 	; r1 = const unsigned char *_src1
michael@0: 	; r2 = const unsigned char *_src2
michael@0: 	; r3 =       int            _ystride
michael@0: 	LDR	r12,[r13]
michael@0: 	; r12= const ogg_int16_t    _residue[64]
michael@0: 	VLDMIA	r12,{D16-D31}
michael@0: 	VLD1.64	{D0}, [r1], r3
michael@0: 	VLD1.64	{D4}, [r2], r3
michael@0: 	VLD1.64	{D1}, [r1], r3
michael@0: 	VLD1.64	{D5}, [r2], r3
michael@0: 	VHADD.U8	Q2, Q0, Q2	; Q2 = FFEEDDCCBBAA99887766554433221100
michael@0: 	VLD1.64	{D2}, [r1], r3
michael@0: 	VLD1.64	{D6}, [r2], r3
michael@0: 	VMOVL.U8	Q0, D4		; Q0 = __77__66__55__44__33__22__11__00
michael@0: 	VLD1.64	{D3}, [r1], r3
michael@0: 	VMOVL.U8	Q2, D5		; etc
michael@0: 	VLD1.64	{D7}, [r2], r3
michael@0: 	VHADD.U8	Q3, Q1, Q3
michael@0: 	VQADD.S16	Q8, Q8, Q0
michael@0: 	VQADD.S16	Q9, Q9, Q2
michael@0: 	VLD1.64	{D0}, [r1], r3
michael@0: 	VMOVL.U8	Q1, D6
michael@0: 	VLD1.64	{D4}, [r2], r3
michael@0: 	VMOVL.U8	Q3, D7
michael@0: 	VLD1.64	{D1}, [r1], r3
michael@0: 	VQADD.S16	Q10,Q10,Q1
michael@0: 	VLD1.64	{D5}, [r2], r3
michael@0: 	VQADD.S16	Q11,Q11,Q3
michael@0: 	VLD1.64	{D2}, [r1], r3
michael@0: 	VHADD.U8	Q2, Q0, Q2
michael@0: 	VLD1.64	{D6}, [r2], r3
michael@0: 	VLD1.64	{D3}, [r1], r3
michael@0: 	VMOVL.U8	Q0, D4
michael@0: 	VLD1.64	{D7}, [r2], r3
michael@0: 	VMOVL.U8	Q2, D5
michael@0: 	VHADD.U8	Q3, Q1, Q3
michael@0: 	VQADD.S16	Q12,Q12,Q0
michael@0: 	VQADD.S16	Q13,Q13,Q2
michael@0: 	VMOVL.U8	Q1, D6
michael@0: 	VMOVL.U8	Q3, D7
michael@0: 	VQADD.S16	Q14,Q14,Q1
michael@0: 	VQADD.S16	Q15,Q15,Q3
michael@0: 	VQMOVUN.S16	D16,Q8
michael@0: 	VQMOVUN.S16	D17,Q9
michael@0: 	VQMOVUN.S16	D18,Q10
michael@0: 	VST1.64	{D16},[r0@64], r3
michael@0: 	VQMOVUN.S16	D19,Q11
michael@0: 	VST1.64	{D17},[r0@64], r3
michael@0: 	VQMOVUN.S16	D20,Q12
michael@0: 	VST1.64	{D18},[r0@64], r3
michael@0: 	VQMOVUN.S16	D21,Q13
michael@0: 	VST1.64	{D19},[r0@64], r3
michael@0: 	VQMOVUN.S16	D22,Q14
michael@0: 	VST1.64	{D20},[r0@64], r3
michael@0: 	VQMOVUN.S16	D23,Q15
michael@0: 	VST1.64	{D21},[r0@64], r3
michael@0: 	VST1.64	{D22},[r0@64], r3
michael@0: 	VST1.64	{D23},[r0@64], r3
michael@0: 	MOV	PC,R14
michael@0: 	ENDP
michael@0:  ]
michael@0: 
michael@0: 	END