media/libvpx/build/make/thumb.pm@6474c204b198 (annotated)
media/libvpx/build/make/thumb.pm
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
| michael@0 | 1 | #!/usr/bin/perl |
| michael@0 | 2 | ## |
| michael@0 | 3 | ## Copyright (c) 2013 The WebM project authors. All Rights Reserved. |
| michael@0 | 4 | ## |
| michael@0 | 5 | ## Use of this source code is governed by a BSD-style license |
| michael@0 | 6 | ## that can be found in the LICENSE file in the root of the source |
| michael@0 | 7 | ## tree. An additional intellectual property rights grant can be found |
| michael@0 | 8 | ## in the file PATENTS. All contributing project authors may |
| michael@0 | 9 | ## be found in the AUTHORS file in the root of the source tree. |
| michael@0 | 10 | ## |
| michael@0 | 11 | |
| michael@0 | 12 | package thumb; |
| michael@0 | 13 | |
| michael@0 | 14 | sub FixThumbInstructions($$) |
| michael@0 | 15 | { |
| michael@0 | 16 | my $short_branches = $_[1]; |
| michael@0 | 17 | my $branch_shift_offset = $short_branches ? 1 : 0; |
| michael@0 | 18 | |
| michael@0 | 19 | # Write additions with shifts, such as "add r10, r11, lsl #8", |
| michael@0 | 20 | # in three operand form, "add r10, r10, r11, lsl #8". |
| michael@0 | 21 | s/(add\s+)(r\d+),\s*(r\d+),\s*(lsl #\d+)/$1$2, $2, $3, $4/g; |
| michael@0 | 22 | |
| michael@0 | 23 | # Convert additions with a non-constant shift into a sequence |
| michael@0 | 24 | # with left shift, addition and a right shift (to restore the |
| michael@0 | 25 | # register to the original value). Currently the right shift |
| michael@0 | 26 | # isn't necessary in the code base since the values in these |
| michael@0 | 27 | # registers aren't used, but doing the shift for consitency. |
| michael@0 | 28 | # This converts instructions such as "add r12, r12, r5, lsl r4" |
| michael@0 | 29 | # into the sequence "lsl r5, r4", "add r12, r12, r5", "lsr r5, r4". |
| michael@0 | 30 | s/^(\s*)(add)(\s+)(r\d+),\s*(r\d+),\s*(r\d+),\s*lsl (r\d+)/$1lsl$3$6, $7\n$1$2$3$4, $5, $6\n$1lsr$3$6, $7/g; |
| michael@0 | 31 | |
| michael@0 | 32 | # Convert loads with right shifts in the indexing into a |
| michael@0 | 33 | # sequence of an add, load and sub. This converts |
| michael@0 | 34 | # "ldrb r4, [r9, lr, asr #1]" into "add r9, r9, lr, asr #1", |
| michael@0 | 35 | # "ldrb r9, [r9]", "sub r9, r9, lr, asr #1". |
| michael@0 | 36 | s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+),\s*(asr #\d+)\]/$1add $3$5, $5, $6, $7\n$1$2$3$4, [$5]\n$1sub $3$5, $5, $6, $7/g; |
| michael@0 | 37 | |
| michael@0 | 38 | # Convert register indexing with writeback into a separate add |
| michael@0 | 39 | # instruction. This converts "ldrb r12, [r1, r2]!" into |
| michael@0 | 40 | # "ldrb r12, [r1, r2]", "add r1, r1, r2". |
| michael@0 | 41 | s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+)\]!/$1$2$3$4, [$5, $6]\n$1add $3$5, $6/g; |
| michael@0 | 42 | |
| michael@0 | 43 | # Convert negative register indexing into separate sub/add instructions. |
| michael@0 | 44 | # This converts "ldrne r4, [src, -pstep, lsl #1]" into |
| michael@0 | 45 | # "subne src, src, pstep, lsl #1", "ldrne r4, [src]", |
| michael@0 | 46 | # "addne src, src, pstep, lsl #1". In a couple of cases where |
| michael@0 | 47 | # this is used, it's used for two subsequent load instructions, |
| michael@0 | 48 | # where a hand-written version of it could merge two subsequent |
| michael@0 | 49 | # add and sub instructions. |
| michael@0 | 50 | s/^(\s*)((ldr|str|pld)(ne)?)(\s+)(r\d+,\s*)?\[(\w+), -([^\]]+)\]/$1sub$4$5$7, $7, $8\n$1$2$5$6\[$7\]\n$1add$4$5$7, $7, $8/g; |
| michael@0 | 51 | |
| michael@0 | 52 | # Convert register post indexing to a separate add instruction. |
| michael@0 | 53 | # This converts "ldrneb r9, [r0], r2" into "ldrneb r9, [r0]", |
| michael@0 | 54 | # "add r0, r2". |
| michael@0 | 55 | s/^(\s*)((ldr|str)(ne)?[bhd]?)(\s+)(\w+),(\s*\w+,)?\s*\[(\w+)\],\s*(\w+)/$1$2$5$6,$7 [$8]\n$1add$4$5$8, $8, $9/g; |
| michael@0 | 56 | |
| michael@0 | 57 | # Convert a conditional addition to the pc register into a series of |
| michael@0 | 58 | # instructions. This converts "addlt pc, pc, r3, lsl #2" into |
| michael@0 | 59 | # "itttt lt", "movlt.n r12, pc", "addlt.w r12, #12", |
| michael@0 | 60 | # "addlt.w r12, r12, r3, lsl #2", "movlt.n pc, r12". |
| michael@0 | 61 | # This assumes that r12 is free at this point. |
| michael@0 | 62 | s/^(\s*)addlt(\s+)pc,\s*pc,\s*(\w+),\s*lsl\s*#(\d+)/$1itttt$2lt\n$1movlt.n$2r12, pc\n$1addlt.w$2r12, #12\n$1addlt.w$2r12, r12, $3, lsl #($4-$branch_shift_offset)\n$1movlt.n$2pc, r12/g; |
| michael@0 | 63 | |
| michael@0 | 64 | # Convert "mov pc, lr" into "bx lr", since the former only works |
| michael@0 | 65 | # for switching from arm to thumb (and only in armv7), but not |
| michael@0 | 66 | # from thumb to arm. |
| michael@0 | 67 | s/mov(\s*)pc\s*,\s*lr/bx$1lr/g; |
| michael@0 | 68 | } |
| michael@0 | 69 | |
| michael@0 | 70 | 1; |
