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media/libvpx/vp8/encoder/arm/neon/subtract_neon.asm@ac0c01689b40 (annotated)

media/libvpx/vp8/encoder/arm/neon/subtract_neon.asm

Thu, 15 Jan 2015 15:59:08 +0100

author

Michael Schloh von Bennewitz <michael@schloh.com>

date

Thu, 15 Jan 2015 15:59:08 +0100

branch

TOR_BUG_9701

changeset 10

ac0c01689b40

permissions

-rw-r--r--

Implement a real Private Browsing Mode condition by changing the API/ABI;
This solves Tor bug #9701, complying with disk avoidance documented in
https://www.torproject.org/projects/torbrowser/design/#disk-avoidance.

michael@0	1	;
michael@0	2	; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
michael@0	3	;
michael@0	4	; Use of this source code is governed by a BSD-style license
michael@0	5	; that can be found in the LICENSE file in the root of the source
michael@0	6	; tree. An additional intellectual property rights grant can be found
michael@0	7	; in the file PATENTS. All contributing project authors may
michael@0	8	; be found in the AUTHORS file in the root of the source tree.
michael@0	9	;
michael@0	10
michael@0	11	EXPORT |vp8_subtract_b_neon|
michael@0	12	EXPORT |vp8_subtract_mby_neon|
michael@0	13	EXPORT |vp8_subtract_mbuv_neon|
michael@0	14
michael@0	15	INCLUDE vp8_asm_enc_offsets.asm
michael@0	16
michael@0	17	ARM
michael@0	18	REQUIRE8
michael@0	19	PRESERVE8
michael@0	20
michael@0	21	AREA ||.text||, CODE, READONLY, ALIGN=2
michael@0	22
michael@0	23	;void vp8_subtract_b_neon(BLOCK *be, BLOCKD *bd, int pitch)
michael@0	24	|vp8_subtract_b_neon| PROC
michael@0	25
michael@0	26	stmfd sp!, {r4-r7}
michael@0	27
michael@0	28	ldr r3, [r0, #vp8_block_base_src]
michael@0	29	ldr r4, [r0, #vp8_block_src]
michael@0	30	ldr r5, [r0, #vp8_block_src_diff]
michael@0	31	ldr r3, [r3]
michael@0	32	ldr r6, [r0, #vp8_block_src_stride]
michael@0	33	add r3, r3, r4 ; src = *base_src + src
michael@0	34	ldr r7, [r1, #vp8_blockd_predictor]
michael@0	35
michael@0	36	vld1.8 {d0}, [r3], r6 ;load src
michael@0	37	vld1.8 {d1}, [r7], r2 ;load pred
michael@0	38	vld1.8 {d2}, [r3], r6
michael@0	39	vld1.8 {d3}, [r7], r2
michael@0	40	vld1.8 {d4}, [r3], r6
michael@0	41	vld1.8 {d5}, [r7], r2
michael@0	42	vld1.8 {d6}, [r3], r6
michael@0	43	vld1.8 {d7}, [r7], r2
michael@0	44
michael@0	45	vsubl.u8 q10, d0, d1
michael@0	46	vsubl.u8 q11, d2, d3
michael@0	47	vsubl.u8 q12, d4, d5
michael@0	48	vsubl.u8 q13, d6, d7
michael@0	49
michael@0	50	mov r2, r2, lsl #1
michael@0	51
michael@0	52	vst1.16 {d20}, [r5], r2 ;store diff
michael@0	53	vst1.16 {d22}, [r5], r2
michael@0	54	vst1.16 {d24}, [r5], r2
michael@0	55	vst1.16 {d26}, [r5], r2
michael@0	56
michael@0	57	ldmfd sp!, {r4-r7}
michael@0	58	bx lr
michael@0	59
michael@0	60	ENDP
michael@0	61
michael@0	62
michael@0	63	;==========================================
michael@0	64	;void vp8_subtract_mby_neon(short *diff, unsigned char *src, int src_stride
michael@0	65	; unsigned char *pred, int pred_stride)
michael@0	66	|vp8_subtract_mby_neon| PROC
michael@0	67	push {r4-r7}
michael@0	68	mov r12, #4
michael@0	69	ldr r4, [sp, #16] ; pred_stride
michael@0	70	mov r6, #32 ; "diff" stride x2
michael@0	71	add r5, r0, #16 ; second diff pointer
michael@0	72
michael@0	73	subtract_mby_loop
michael@0	74	vld1.8 {q0}, [r1], r2 ;load src
michael@0	75	vld1.8 {q1}, [r3], r4 ;load pred
michael@0	76	vld1.8 {q2}, [r1], r2
michael@0	77	vld1.8 {q3}, [r3], r4
michael@0	78	vld1.8 {q4}, [r1], r2
michael@0	79	vld1.8 {q5}, [r3], r4
michael@0	80	vld1.8 {q6}, [r1], r2
michael@0	81	vld1.8 {q7}, [r3], r4
michael@0	82
michael@0	83	vsubl.u8 q8, d0, d2
michael@0	84	vsubl.u8 q9, d1, d3
michael@0	85	vsubl.u8 q10, d4, d6
michael@0	86	vsubl.u8 q11, d5, d7
michael@0	87	vsubl.u8 q12, d8, d10
michael@0	88	vsubl.u8 q13, d9, d11
michael@0	89	vsubl.u8 q14, d12, d14
michael@0	90	vsubl.u8 q15, d13, d15
michael@0	91
michael@0	92	vst1.16 {q8}, [r0], r6 ;store diff
michael@0	93	vst1.16 {q9}, [r5], r6
michael@0	94	vst1.16 {q10}, [r0], r6
michael@0	95	vst1.16 {q11}, [r5], r6
michael@0	96	vst1.16 {q12}, [r0], r6
michael@0	97	vst1.16 {q13}, [r5], r6
michael@0	98	vst1.16 {q14}, [r0], r6
michael@0	99	vst1.16 {q15}, [r5], r6
michael@0	100
michael@0	101	subs r12, r12, #1
michael@0	102	bne subtract_mby_loop
michael@0	103
michael@0	104	pop {r4-r7}
michael@0	105	bx lr
michael@0	106	ENDP
michael@0	107
michael@0	108	;=================================
michael@0	109	;void vp8_subtract_mbuv_c(short *diff, unsigned char *usrc, unsigned char *vsrc,
michael@0	110	; int src_stride, unsigned char *upred,
michael@0	111	; unsigned char *vpred, int pred_stride)
michael@0	112
michael@0	113	|vp8_subtract_mbuv_neon| PROC
michael@0	114	push {r4-r7}
michael@0	115	ldr r4, [sp, #16] ; upred
michael@0	116	ldr r5, [sp, #20] ; vpred
michael@0	117	ldr r6, [sp, #24] ; pred_stride
michael@0	118	add r0, r0, #512 ; short *udiff = diff + 256;
michael@0	119	mov r12, #32 ; "diff" stride x2
michael@0	120	add r7, r0, #16 ; second diff pointer
michael@0	121
michael@0	122	;u
michael@0	123	vld1.8 {d0}, [r1], r3 ;load usrc
michael@0	124	vld1.8 {d1}, [r4], r6 ;load upred
michael@0	125	vld1.8 {d2}, [r1], r3
michael@0	126	vld1.8 {d3}, [r4], r6
michael@0	127	vld1.8 {d4}, [r1], r3
michael@0	128	vld1.8 {d5}, [r4], r6
michael@0	129	vld1.8 {d6}, [r1], r3
michael@0	130	vld1.8 {d7}, [r4], r6
michael@0	131	vld1.8 {d8}, [r1], r3
michael@0	132	vld1.8 {d9}, [r4], r6
michael@0	133	vld1.8 {d10}, [r1], r3
michael@0	134	vld1.8 {d11}, [r4], r6
michael@0	135	vld1.8 {d12}, [r1], r3
michael@0	136	vld1.8 {d13}, [r4], r6
michael@0	137	vld1.8 {d14}, [r1], r3
michael@0	138	vld1.8 {d15}, [r4], r6
michael@0	139
michael@0	140	vsubl.u8 q8, d0, d1
michael@0	141	vsubl.u8 q9, d2, d3
michael@0	142	vsubl.u8 q10, d4, d5
michael@0	143	vsubl.u8 q11, d6, d7
michael@0	144	vsubl.u8 q12, d8, d9
michael@0	145	vsubl.u8 q13, d10, d11
michael@0	146	vsubl.u8 q14, d12, d13
michael@0	147	vsubl.u8 q15, d14, d15
michael@0	148
michael@0	149	vst1.16 {q8}, [r0], r12 ;store diff
michael@0	150	vst1.16 {q9}, [r7], r12
michael@0	151	vst1.16 {q10}, [r0], r12
michael@0	152	vst1.16 {q11}, [r7], r12
michael@0	153	vst1.16 {q12}, [r0], r12
michael@0	154	vst1.16 {q13}, [r7], r12
michael@0	155	vst1.16 {q14}, [r0], r12
michael@0	156	vst1.16 {q15}, [r7], r12
michael@0	157
michael@0	158	;v
michael@0	159	vld1.8 {d0}, [r2], r3 ;load vsrc
michael@0	160	vld1.8 {d1}, [r5], r6 ;load vpred
michael@0	161	vld1.8 {d2}, [r2], r3
michael@0	162	vld1.8 {d3}, [r5], r6
michael@0	163	vld1.8 {d4}, [r2], r3
michael@0	164	vld1.8 {d5}, [r5], r6
michael@0	165	vld1.8 {d6}, [r2], r3
michael@0	166	vld1.8 {d7}, [r5], r6
michael@0	167	vld1.8 {d8}, [r2], r3
michael@0	168	vld1.8 {d9}, [r5], r6
michael@0	169	vld1.8 {d10}, [r2], r3
michael@0	170	vld1.8 {d11}, [r5], r6
michael@0	171	vld1.8 {d12}, [r2], r3
michael@0	172	vld1.8 {d13}, [r5], r6
michael@0	173	vld1.8 {d14}, [r2], r3
michael@0	174	vld1.8 {d15}, [r5], r6
michael@0	175
michael@0	176	vsubl.u8 q8, d0, d1
michael@0	177	vsubl.u8 q9, d2, d3
michael@0	178	vsubl.u8 q10, d4, d5
michael@0	179	vsubl.u8 q11, d6, d7
michael@0	180	vsubl.u8 q12, d8, d9
michael@0	181	vsubl.u8 q13, d10, d11
michael@0	182	vsubl.u8 q14, d12, d13
michael@0	183	vsubl.u8 q15, d14, d15
michael@0	184
michael@0	185	vst1.16 {q8}, [r0], r12 ;store diff
michael@0	186	vst1.16 {q9}, [r7], r12
michael@0	187	vst1.16 {q10}, [r0], r12
michael@0	188	vst1.16 {q11}, [r7], r12
michael@0	189	vst1.16 {q12}, [r0], r12
michael@0	190	vst1.16 {q13}, [r7], r12
michael@0	191	vst1.16 {q14}, [r0], r12
michael@0	192	vst1.16 {q15}, [r7], r12
michael@0	193
michael@0	194	pop {r4-r7}
michael@0	195	bx lr
michael@0	196
michael@0	197	ENDP
michael@0	198
michael@0	199	END