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comparison: ipc/chromium/src/base/atomicops.h
ipc/chromium/src/base/atomicops.h
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| 1 // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. | |
| 2 // Use of this source code is governed by a BSD-style license that can be | |
| 3 // found in the LICENSE file. | |
| 4 | |
| 5 // For atomic operations on reference counts, see atomic_refcount.h. | |
| 6 // For atomic operations on sequence numbers, see atomic_sequence_num.h. | |
| 7 | |
| 8 // The routines exported by this module are subtle. If you use them, even if | |
| 9 // you get the code right, it will depend on careful reasoning about atomicity | |
| 10 // and memory ordering; it will be less readable, and harder to maintain. If | |
| 11 // you plan to use these routines, you should have a good reason, such as solid | |
| 12 // evidence that performance would otherwise suffer, or there being no | |
| 13 // alternative. You should assume only properties explicitly guaranteed by the | |
| 14 // specifications in this file. You are almost certainly _not_ writing code | |
| 15 // just for the x86; if you assume x86 semantics, x86 hardware bugs and | |
| 16 // implementations on other archtectures will cause your code to break. If you | |
| 17 // do not know what you are doing, avoid these routines, and use a Mutex. | |
| 18 // | |
| 19 // It is incorrect to make direct assignments to/from an atomic variable. | |
| 20 // You should use one of the Load or Store routines. The NoBarrier | |
| 21 // versions are provided when no barriers are needed: | |
| 22 // NoBarrier_Store() | |
| 23 // NoBarrier_Load() | |
| 24 // Although there are currently no compiler enforcement, you are encouraged | |
| 25 // to use these. | |
| 26 // | |
| 27 | |
| 28 #ifndef BASE_ATOMICOPS_H_ | |
| 29 #define BASE_ATOMICOPS_H_ | |
| 30 | |
| 31 #include "base/basictypes.h" | |
| 32 #include "base/port.h" | |
| 33 | |
| 34 namespace base { | |
| 35 namespace subtle { | |
| 36 | |
| 37 // Bug 1308991. We need this for /Wp64, to mark it safe for AtomicWord casting. | |
| 38 #ifndef OS_WIN | |
| 39 #define __w64 | |
| 40 #endif | |
| 41 typedef __w64 int32_t Atomic32; | |
| 42 #ifdef ARCH_CPU_64_BITS | |
| 43 typedef int64_t Atomic64; | |
| 44 #endif | |
| 45 | |
| 46 // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or | |
| 47 // Atomic64 routines below, depending on your architecture. | |
| 48 #ifdef OS_OPENBSD | |
| 49 #ifdef ARCH_CPU_64_BITS | |
| 50 typedef Atomic64 AtomicWord; | |
| 51 #else | |
| 52 typedef Atomic32 AtomicWord; | |
| 53 #endif // ARCH_CPU_64_BITS | |
| 54 #else | |
| 55 typedef intptr_t AtomicWord; | |
| 56 #endif // OS_OPENBSD | |
| 57 | |
| 58 // Atomically execute: | |
| 59 // result = *ptr; | |
| 60 // if (*ptr == old_value) | |
| 61 // *ptr = new_value; | |
| 62 // return result; | |
| 63 // | |
| 64 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value". | |
| 65 // Always return the old value of "*ptr" | |
| 66 // | |
| 67 // This routine implies no memory barriers. | |
| 68 Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, | |
| 69 Atomic32 old_value, | |
| 70 Atomic32 new_value); | |
| 71 | |
| 72 // Atomically store new_value into *ptr, returning the previous value held in | |
| 73 // *ptr. This routine implies no memory barriers. | |
| 74 Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value); | |
| 75 | |
| 76 // Atomically increment *ptr by "increment". Returns the new value of | |
| 77 // *ptr with the increment applied. This routine implies no memory barriers. | |
| 78 Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment); | |
| 79 | |
| 80 Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, | |
| 81 Atomic32 increment); | |
| 82 | |
| 83 // These following lower-level operations are typically useful only to people | |
| 84 // implementing higher-level synchronization operations like spinlocks, | |
| 85 // mutexes, and condition-variables. They combine CompareAndSwap(), a load, or | |
| 86 // a store with appropriate memory-ordering instructions. "Acquire" operations | |
| 87 // ensure that no later memory access can be reordered ahead of the operation. | |
| 88 // "Release" operations ensure that no previous memory access can be reordered | |
| 89 // after the operation. "Barrier" operations have both "Acquire" and "Release" | |
| 90 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory | |
| 91 // access. | |
| 92 Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, | |
| 93 Atomic32 old_value, | |
| 94 Atomic32 new_value); | |
| 95 Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, | |
| 96 Atomic32 old_value, | |
| 97 Atomic32 new_value); | |
| 98 | |
| 99 void MemoryBarrier(); | |
| 100 void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value); | |
| 101 void Acquire_Store(volatile Atomic32* ptr, Atomic32 value); | |
| 102 void Release_Store(volatile Atomic32* ptr, Atomic32 value); | |
| 103 | |
| 104 Atomic32 NoBarrier_Load(volatile const Atomic32* ptr); | |
| 105 Atomic32 Acquire_Load(volatile const Atomic32* ptr); | |
| 106 Atomic32 Release_Load(volatile const Atomic32* ptr); | |
| 107 | |
| 108 // 64-bit atomic operations (only available on 64-bit processors). | |
| 109 #ifdef ARCH_CPU_64_BITS | |
| 110 Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, | |
| 111 Atomic64 old_value, | |
| 112 Atomic64 new_value); | |
| 113 Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value); | |
| 114 Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); | |
| 115 Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); | |
| 116 | |
| 117 Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, | |
| 118 Atomic64 old_value, | |
| 119 Atomic64 new_value); | |
| 120 Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, | |
| 121 Atomic64 old_value, | |
| 122 Atomic64 new_value); | |
| 123 void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value); | |
| 124 void Acquire_Store(volatile Atomic64* ptr, Atomic64 value); | |
| 125 void Release_Store(volatile Atomic64* ptr, Atomic64 value); | |
| 126 Atomic64 NoBarrier_Load(volatile const Atomic64* ptr); | |
| 127 Atomic64 Acquire_Load(volatile const Atomic64* ptr); | |
| 128 Atomic64 Release_Load(volatile const Atomic64* ptr); | |
| 129 #endif // CPU_ARCH_64_BITS | |
| 130 | |
| 131 } // namespace base::subtle | |
| 132 } // namespace base | |
| 133 | |
| 134 // Include our platform specific implementation. | |
| 135 #if defined(OS_WIN) && defined(ARCH_CPU_X86_FAMILY) | |
| 136 #include "base/atomicops_internals_x86_msvc.h" | |
| 137 #elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY) | |
| 138 #include "base/atomicops_internals_x86_macosx.h" | |
| 139 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY) | |
| 140 #include "base/atomicops_internals_x86_gcc.h" | |
| 141 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY) | |
| 142 #include "base/atomicops_internals_arm_gcc.h" | |
| 143 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS) | |
| 144 #include "base/atomicops_internals_mips_gcc.h" | |
| 145 #else | |
| 146 #include "base/atomicops_internals_mutex.h" | |
| 147 #endif | |
| 148 | |
| 149 #endif // BASE_ATOMICOPS_H_ |
