ipc/chromium/src/base/atomicops.h@6474c204b198 (annotated)
ipc/chromium/src/base/atomicops.h
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
| michael@0 | 1 | // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. |
| michael@0 | 2 | // Use of this source code is governed by a BSD-style license that can be |
| michael@0 | 3 | // found in the LICENSE file. |
| michael@0 | 4 | |
| michael@0 | 5 | // For atomic operations on reference counts, see atomic_refcount.h. |
| michael@0 | 6 | // For atomic operations on sequence numbers, see atomic_sequence_num.h. |
| michael@0 | 7 | |
| michael@0 | 8 | // The routines exported by this module are subtle. If you use them, even if |
| michael@0 | 9 | // you get the code right, it will depend on careful reasoning about atomicity |
| michael@0 | 10 | // and memory ordering; it will be less readable, and harder to maintain. If |
| michael@0 | 11 | // you plan to use these routines, you should have a good reason, such as solid |
| michael@0 | 12 | // evidence that performance would otherwise suffer, or there being no |
| michael@0 | 13 | // alternative. You should assume only properties explicitly guaranteed by the |
| michael@0 | 14 | // specifications in this file. You are almost certainly _not_ writing code |
| michael@0 | 15 | // just for the x86; if you assume x86 semantics, x86 hardware bugs and |
| michael@0 | 16 | // implementations on other archtectures will cause your code to break. If you |
| michael@0 | 17 | // do not know what you are doing, avoid these routines, and use a Mutex. |
| michael@0 | 18 | // |
| michael@0 | 19 | // It is incorrect to make direct assignments to/from an atomic variable. |
| michael@0 | 20 | // You should use one of the Load or Store routines. The NoBarrier |
| michael@0 | 21 | // versions are provided when no barriers are needed: |
| michael@0 | 22 | // NoBarrier_Store() |
| michael@0 | 23 | // NoBarrier_Load() |
| michael@0 | 24 | // Although there are currently no compiler enforcement, you are encouraged |
| michael@0 | 25 | // to use these. |
| michael@0 | 26 | // |
| michael@0 | 27 | |
| michael@0 | 28 | #ifndef BASE_ATOMICOPS_H_ |
| michael@0 | 29 | #define BASE_ATOMICOPS_H_ |
| michael@0 | 30 | |
| michael@0 | 31 | #include "base/basictypes.h" |
| michael@0 | 32 | #include "base/port.h" |
| michael@0 | 33 | |
| michael@0 | 34 | namespace base { |
| michael@0 | 35 | namespace subtle { |
| michael@0 | 36 | |
| michael@0 | 37 | // Bug 1308991. We need this for /Wp64, to mark it safe for AtomicWord casting. |
| michael@0 | 38 | #ifndef OS_WIN |
| michael@0 | 39 | #define __w64 |
| michael@0 | 40 | #endif |
| michael@0 | 41 | typedef __w64 int32_t Atomic32; |
| michael@0 | 42 | #ifdef ARCH_CPU_64_BITS |
| michael@0 | 43 | typedef int64_t Atomic64; |
| michael@0 | 44 | #endif |
| michael@0 | 45 | |
| michael@0 | 46 | // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or |
| michael@0 | 47 | // Atomic64 routines below, depending on your architecture. |
| michael@0 | 48 | #ifdef OS_OPENBSD |
| michael@0 | 49 | #ifdef ARCH_CPU_64_BITS |
| michael@0 | 50 | typedef Atomic64 AtomicWord; |
| michael@0 | 51 | #else |
| michael@0 | 52 | typedef Atomic32 AtomicWord; |
| michael@0 | 53 | #endif // ARCH_CPU_64_BITS |
| michael@0 | 54 | #else |
| michael@0 | 55 | typedef intptr_t AtomicWord; |
| michael@0 | 56 | #endif // OS_OPENBSD |
| michael@0 | 57 | |
| michael@0 | 58 | // Atomically execute: |
| michael@0 | 59 | // result = *ptr; |
| michael@0 | 60 | // if (*ptr == old_value) |
| michael@0 | 61 | // *ptr = new_value; |
| michael@0 | 62 | // return result; |
| michael@0 | 63 | // |
| michael@0 | 64 | // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value". |
| michael@0 | 65 | // Always return the old value of "*ptr" |
| michael@0 | 66 | // |
| michael@0 | 67 | // This routine implies no memory barriers. |
| michael@0 | 68 | Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, |
| michael@0 | 69 | Atomic32 old_value, |
| michael@0 | 70 | Atomic32 new_value); |
| michael@0 | 71 | |
| michael@0 | 72 | // Atomically store new_value into *ptr, returning the previous value held in |
| michael@0 | 73 | // *ptr. This routine implies no memory barriers. |
| michael@0 | 74 | Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value); |
| michael@0 | 75 | |
| michael@0 | 76 | // Atomically increment *ptr by "increment". Returns the new value of |
| michael@0 | 77 | // *ptr with the increment applied. This routine implies no memory barriers. |
| michael@0 | 78 | Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment); |
| michael@0 | 79 | |
| michael@0 | 80 | Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, |
| michael@0 | 81 | Atomic32 increment); |
| michael@0 | 82 | |
| michael@0 | 83 | // These following lower-level operations are typically useful only to people |
| michael@0 | 84 | // implementing higher-level synchronization operations like spinlocks, |
| michael@0 | 85 | // mutexes, and condition-variables. They combine CompareAndSwap(), a load, or |
| michael@0 | 86 | // a store with appropriate memory-ordering instructions. "Acquire" operations |
| michael@0 | 87 | // ensure that no later memory access can be reordered ahead of the operation. |
| michael@0 | 88 | // "Release" operations ensure that no previous memory access can be reordered |
| michael@0 | 89 | // after the operation. "Barrier" operations have both "Acquire" and "Release" |
| michael@0 | 90 | // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory |
| michael@0 | 91 | // access. |
| michael@0 | 92 | Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, |
| michael@0 | 93 | Atomic32 old_value, |
| michael@0 | 94 | Atomic32 new_value); |
| michael@0 | 95 | Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, |
| michael@0 | 96 | Atomic32 old_value, |
| michael@0 | 97 | Atomic32 new_value); |
| michael@0 | 98 | |
| michael@0 | 99 | void MemoryBarrier(); |
| michael@0 | 100 | void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value); |
| michael@0 | 101 | void Acquire_Store(volatile Atomic32* ptr, Atomic32 value); |
| michael@0 | 102 | void Release_Store(volatile Atomic32* ptr, Atomic32 value); |
| michael@0 | 103 | |
| michael@0 | 104 | Atomic32 NoBarrier_Load(volatile const Atomic32* ptr); |
| michael@0 | 105 | Atomic32 Acquire_Load(volatile const Atomic32* ptr); |
| michael@0 | 106 | Atomic32 Release_Load(volatile const Atomic32* ptr); |
| michael@0 | 107 | |
| michael@0 | 108 | // 64-bit atomic operations (only available on 64-bit processors). |
| michael@0 | 109 | #ifdef ARCH_CPU_64_BITS |
| michael@0 | 110 | Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, |
| michael@0 | 111 | Atomic64 old_value, |
| michael@0 | 112 | Atomic64 new_value); |
| michael@0 | 113 | Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value); |
| michael@0 | 114 | Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); |
| michael@0 | 115 | Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); |
| michael@0 | 116 | |
| michael@0 | 117 | Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, |
| michael@0 | 118 | Atomic64 old_value, |
| michael@0 | 119 | Atomic64 new_value); |
| michael@0 | 120 | Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, |
| michael@0 | 121 | Atomic64 old_value, |
| michael@0 | 122 | Atomic64 new_value); |
| michael@0 | 123 | void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value); |
| michael@0 | 124 | void Acquire_Store(volatile Atomic64* ptr, Atomic64 value); |
| michael@0 | 125 | void Release_Store(volatile Atomic64* ptr, Atomic64 value); |
| michael@0 | 126 | Atomic64 NoBarrier_Load(volatile const Atomic64* ptr); |
| michael@0 | 127 | Atomic64 Acquire_Load(volatile const Atomic64* ptr); |
| michael@0 | 128 | Atomic64 Release_Load(volatile const Atomic64* ptr); |
| michael@0 | 129 | #endif // CPU_ARCH_64_BITS |
| michael@0 | 130 | |
| michael@0 | 131 | } // namespace base::subtle |
| michael@0 | 132 | } // namespace base |
| michael@0 | 133 | |
| michael@0 | 134 | // Include our platform specific implementation. |
| michael@0 | 135 | #if defined(OS_WIN) && defined(ARCH_CPU_X86_FAMILY) |
| michael@0 | 136 | #include "base/atomicops_internals_x86_msvc.h" |
| michael@0 | 137 | #elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY) |
| michael@0 | 138 | #include "base/atomicops_internals_x86_macosx.h" |
| michael@0 | 139 | #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY) |
| michael@0 | 140 | #include "base/atomicops_internals_x86_gcc.h" |
| michael@0 | 141 | #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY) |
| michael@0 | 142 | #include "base/atomicops_internals_arm_gcc.h" |
| michael@0 | 143 | #elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS) |
| michael@0 | 144 | #include "base/atomicops_internals_mips_gcc.h" |
| michael@0 | 145 | #else |
| michael@0 | 146 | #include "base/atomicops_internals_mutex.h" |
| michael@0 | 147 | #endif |
| michael@0 | 148 | |
| michael@0 | 149 | #endif // BASE_ATOMICOPS_H_ |
