1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/ipc/chromium/src/base/atomicops_internals_x86_gcc.cc Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,104 @@
1.4 +// Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
1.5 +// Use of this source code is governed by a BSD-style license that can be
1.6 +// found in the LICENSE file.
1.7 +
1.8 +// This module gets enough CPU information to optimize the
1.9 +// atomicops module on x86.
1.10 +
1.11 +#include <string.h>
1.12 +
1.13 +#include "base/atomicops.h"
1.14 +#include "base/basictypes.h"
1.15 +
1.16 +// This file only makes sense with atomicops_internals_x86_gcc.h -- it
1.17 +// depends on structs that are defined in that file. If atomicops.h
1.18 +// doesn't sub-include that file, then we aren't needed, and shouldn't
1.19 +// try to do anything.
1.20 +#ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
1.21 +
1.22 +// Inline cpuid instruction. In PIC compilations, %ebx contains the address
1.23 +// of the global offset table. To avoid breaking such executables, this code
1.24 +// must preserve that register's value across cpuid instructions.
1.25 +#if defined(__i386__)
1.26 +#define cpuid(a, b, c, d, inp) \
1.27 + asm ("mov %%ebx, %%edi\n" \
1.28 + "cpuid\n" \
1.29 + "xchg %%edi, %%ebx\n" \
1.30 + : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
1.31 +#elif defined (__x86_64__)
1.32 +#define cpuid(a, b, c, d, inp) \
1.33 + asm ("mov %%rbx, %%rdi\n" \
1.34 + "cpuid\n" \
1.35 + "xchg %%rdi, %%rbx\n" \
1.36 + : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
1.37 +#endif
1.38 +
1.39 +#if defined(cpuid) // initialize the struct only on x86
1.40 +
1.41 +// Set the flags so that code will run correctly and conservatively, so even
1.42 +// if we haven't been initialized yet, we're probably single threaded, and our
1.43 +// default values should hopefully be pretty safe.
1.44 +struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
1.45 + false, // bug can't exist before process spawns multiple threads
1.46 + false, // no SSE2
1.47 +};
1.48 +
1.49 +// Initialize the AtomicOps_Internalx86CPUFeatures struct.
1.50 +static void AtomicOps_Internalx86CPUFeaturesInit() {
1.51 + uint32_t eax;
1.52 + uint32_t ebx;
1.53 + uint32_t ecx;
1.54 + uint32_t edx;
1.55 +
1.56 + // Get vendor string (issue CPUID with eax = 0)
1.57 + cpuid(eax, ebx, ecx, edx, 0);
1.58 + char vendor[13];
1.59 + memcpy(vendor, &ebx, 4);
1.60 + memcpy(vendor + 4, &edx, 4);
1.61 + memcpy(vendor + 8, &ecx, 4);
1.62 + vendor[12] = 0;
1.63 +
1.64 + // get feature flags in ecx/edx, and family/model in eax
1.65 + cpuid(eax, ebx, ecx, edx, 1);
1.66 +
1.67 + int family = (eax >> 8) & 0xf; // family and model fields
1.68 + int model = (eax >> 4) & 0xf;
1.69 + if (family == 0xf) { // use extended family and model fields
1.70 + family += (eax >> 20) & 0xff;
1.71 + model += ((eax >> 16) & 0xf) << 4;
1.72 + }
1.73 +
1.74 + // Opteron Rev E has a bug in which on very rare occasions a locked
1.75 + // instruction doesn't act as a read-acquire barrier if followed by a
1.76 + // non-locked read-modify-write instruction. Rev F has this bug in
1.77 + // pre-release versions, but not in versions released to customers,
1.78 + // so we test only for Rev E, which is family 15, model 32..63 inclusive.
1.79 + if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD
1.80 + family == 15 &&
1.81 + 32 <= model && model <= 63) {
1.82 + AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
1.83 + } else {
1.84 + AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
1.85 + }
1.86 +
1.87 + // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
1.88 + AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
1.89 +}
1.90 +
1.91 +namespace {
1.92 +
1.93 +class AtomicOpsx86Initializer {
1.94 + public:
1.95 + AtomicOpsx86Initializer() {
1.96 + AtomicOps_Internalx86CPUFeaturesInit();
1.97 + }
1.98 +};
1.99 +
1.100 +// A global to get use initialized on startup via static initialization :/
1.101 +AtomicOpsx86Initializer g_initer;
1.102 +
1.103 +} // namespace
1.104 +
1.105 +#endif // if x86
1.106 +
1.107 +#endif // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
