ipc/chromium/src/base/atomicops_internals_x86_gcc.cc@6474c204b198 (annotated)
ipc/chromium/src/base/atomicops_internals_x86_gcc.cc
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
| michael@0 | 1 | // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. |
| michael@0 | 2 | // Use of this source code is governed by a BSD-style license that can be |
| michael@0 | 3 | // found in the LICENSE file. |
| michael@0 | 4 | |
| michael@0 | 5 | // This module gets enough CPU information to optimize the |
| michael@0 | 6 | // atomicops module on x86. |
| michael@0 | 7 | |
| michael@0 | 8 | #include <string.h> |
| michael@0 | 9 | |
| michael@0 | 10 | #include "base/atomicops.h" |
| michael@0 | 11 | #include "base/basictypes.h" |
| michael@0 | 12 | |
| michael@0 | 13 | // This file only makes sense with atomicops_internals_x86_gcc.h -- it |
| michael@0 | 14 | // depends on structs that are defined in that file. If atomicops.h |
| michael@0 | 15 | // doesn't sub-include that file, then we aren't needed, and shouldn't |
| michael@0 | 16 | // try to do anything. |
| michael@0 | 17 | #ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ |
| michael@0 | 18 | |
| michael@0 | 19 | // Inline cpuid instruction. In PIC compilations, %ebx contains the address |
| michael@0 | 20 | // of the global offset table. To avoid breaking such executables, this code |
| michael@0 | 21 | // must preserve that register's value across cpuid instructions. |
| michael@0 | 22 | #if defined(__i386__) |
| michael@0 | 23 | #define cpuid(a, b, c, d, inp) \ |
| michael@0 | 24 | asm ("mov %%ebx, %%edi\n" \ |
| michael@0 | 25 | "cpuid\n" \ |
| michael@0 | 26 | "xchg %%edi, %%ebx\n" \ |
| michael@0 | 27 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| michael@0 | 28 | #elif defined (__x86_64__) |
| michael@0 | 29 | #define cpuid(a, b, c, d, inp) \ |
| michael@0 | 30 | asm ("mov %%rbx, %%rdi\n" \ |
| michael@0 | 31 | "cpuid\n" \ |
| michael@0 | 32 | "xchg %%rdi, %%rbx\n" \ |
| michael@0 | 33 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| michael@0 | 34 | #endif |
| michael@0 | 35 | |
| michael@0 | 36 | #if defined(cpuid) // initialize the struct only on x86 |
| michael@0 | 37 | |
| michael@0 | 38 | // Set the flags so that code will run correctly and conservatively, so even |
| michael@0 | 39 | // if we haven't been initialized yet, we're probably single threaded, and our |
| michael@0 | 40 | // default values should hopefully be pretty safe. |
| michael@0 | 41 | struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { |
| michael@0 | 42 | false, // bug can't exist before process spawns multiple threads |
| michael@0 | 43 | false, // no SSE2 |
| michael@0 | 44 | }; |
| michael@0 | 45 | |
| michael@0 | 46 | // Initialize the AtomicOps_Internalx86CPUFeatures struct. |
| michael@0 | 47 | static void AtomicOps_Internalx86CPUFeaturesInit() { |
| michael@0 | 48 | uint32_t eax; |
| michael@0 | 49 | uint32_t ebx; |
| michael@0 | 50 | uint32_t ecx; |
| michael@0 | 51 | uint32_t edx; |
| michael@0 | 52 | |
| michael@0 | 53 | // Get vendor string (issue CPUID with eax = 0) |
| michael@0 | 54 | cpuid(eax, ebx, ecx, edx, 0); |
| michael@0 | 55 | char vendor[13]; |
| michael@0 | 56 | memcpy(vendor, &ebx, 4); |
| michael@0 | 57 | memcpy(vendor + 4, &edx, 4); |
| michael@0 | 58 | memcpy(vendor + 8, &ecx, 4); |
| michael@0 | 59 | vendor[12] = 0; |
| michael@0 | 60 | |
| michael@0 | 61 | // get feature flags in ecx/edx, and family/model in eax |
| michael@0 | 62 | cpuid(eax, ebx, ecx, edx, 1); |
| michael@0 | 63 | |
| michael@0 | 64 | int family = (eax >> 8) & 0xf; // family and model fields |
| michael@0 | 65 | int model = (eax >> 4) & 0xf; |
| michael@0 | 66 | if (family == 0xf) { // use extended family and model fields |
| michael@0 | 67 | family += (eax >> 20) & 0xff; |
| michael@0 | 68 | model += ((eax >> 16) & 0xf) << 4; |
| michael@0 | 69 | } |
| michael@0 | 70 | |
| michael@0 | 71 | // Opteron Rev E has a bug in which on very rare occasions a locked |
| michael@0 | 72 | // instruction doesn't act as a read-acquire barrier if followed by a |
| michael@0 | 73 | // non-locked read-modify-write instruction. Rev F has this bug in |
| michael@0 | 74 | // pre-release versions, but not in versions released to customers, |
| michael@0 | 75 | // so we test only for Rev E, which is family 15, model 32..63 inclusive. |
| michael@0 | 76 | if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD |
| michael@0 | 77 | family == 15 && |
| michael@0 | 78 | 32 <= model && model <= 63) { |
| michael@0 | 79 | AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; |
| michael@0 | 80 | } else { |
| michael@0 | 81 | AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; |
| michael@0 | 82 | } |
| michael@0 | 83 | |
| michael@0 | 84 | // edx bit 26 is SSE2 which we use to tell use whether we can use mfence |
| michael@0 | 85 | AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); |
| michael@0 | 86 | } |
| michael@0 | 87 | |
| michael@0 | 88 | namespace { |
| michael@0 | 89 | |
| michael@0 | 90 | class AtomicOpsx86Initializer { |
| michael@0 | 91 | public: |
| michael@0 | 92 | AtomicOpsx86Initializer() { |
| michael@0 | 93 | AtomicOps_Internalx86CPUFeaturesInit(); |
| michael@0 | 94 | } |
| michael@0 | 95 | }; |
| michael@0 | 96 | |
| michael@0 | 97 | // A global to get use initialized on startup via static initialization :/ |
| michael@0 | 98 | AtomicOpsx86Initializer g_initer; |
| michael@0 | 99 | |
| michael@0 | 100 | } // namespace |
| michael@0 | 101 | |
| michael@0 | 102 | #endif // if x86 |
| michael@0 | 103 | |
| michael@0 | 104 | #endif // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ |
