1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/toolkit/crashreporter/google-breakpad/src/third_party/libdisasm/ia32_reg.c Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,234 @@
1.4 +#include <stdlib.h>
1.5 +#include <string.h>
1.6 +
1.7 +#include "ia32_reg.h"
1.8 +#include "ia32_insn.h"
1.9 +
1.10 +#define NUM_X86_REGS 92
1.11 +
1.12 +/* register sizes */
1.13 +#define REG_DWORD_SIZE 4
1.14 +#define REG_WORD_SIZE 2
1.15 +#define REG_BYTE_SIZE 1
1.16 +#define REG_MMX_SIZE 8
1.17 +#define REG_SIMD_SIZE 16
1.18 +#define REG_DEBUG_SIZE 4
1.19 +#define REG_CTRL_SIZE 4
1.20 +#define REG_TEST_SIZE 4
1.21 +#define REG_SEG_SIZE 2
1.22 +#define REG_FPU_SIZE 10
1.23 +#define REG_FLAGS_SIZE 4
1.24 +#define REG_FPCTRL_SIZE 2
1.25 +#define REG_FPSTATUS_SIZE 2
1.26 +#define REG_FPTAG_SIZE 2
1.27 +#define REG_EIP_SIZE 4
1.28 +#define REG_IP_SIZE 2
1.29 +
1.30 +/* REGISTER ALIAS TABLE:
1.31 + *
1.32 + * NOTE: the MMX register mapping is fixed to the physical registers
1.33 + * used by the FPU. The floating FP stack does not effect the location
1.34 + * of the MMX registers, so this aliasing is not 100% accurate.
1.35 + * */
1.36 +static struct {
1.37 + unsigned char alias; /* id of register this is an alias for */
1.38 + unsigned char shift; /* # of bits register must be shifted */
1.39 +} ia32_reg_aliases[] = {
1.40 + { 0,0 },
1.41 + { REG_DWORD_OFFSET, 0 }, /* al : 1 */
1.42 + { REG_DWORD_OFFSET, 8 }, /* ah : 2 */
1.43 + { REG_DWORD_OFFSET, 0 }, /* ax : 3 */
1.44 + { REG_DWORD_OFFSET + 1, 0 }, /* cl : 4 */
1.45 + { REG_DWORD_OFFSET + 1, 8 }, /* ch : 5 */
1.46 + { REG_DWORD_OFFSET + 1, 0 }, /* cx : 6 */
1.47 + { REG_DWORD_OFFSET + 2, 0 }, /* dl : 7 */
1.48 + { REG_DWORD_OFFSET + 2, 8 }, /* dh : 8 */
1.49 + { REG_DWORD_OFFSET + 2, 0 }, /* dx : 9 */
1.50 + { REG_DWORD_OFFSET + 3, 0 }, /* bl : 10 */
1.51 + { REG_DWORD_OFFSET + 3, 8 }, /* bh : 11 */
1.52 + { REG_DWORD_OFFSET + 3, 0 }, /* bx : 12 */
1.53 + { REG_DWORD_OFFSET + 4, 0 }, /* sp : 13 */
1.54 + { REG_DWORD_OFFSET + 5, 0 }, /* bp : 14 */
1.55 + { REG_DWORD_OFFSET + 6, 0 }, /* si : 15 */
1.56 + { REG_DWORD_OFFSET + 7, 0 }, /* di : 16 */
1.57 + { REG_EIP_INDEX, 0 }, /* ip : 17 */
1.58 + { REG_FPU_OFFSET, 0 }, /* mm0 : 18 */
1.59 + { REG_FPU_OFFSET + 1, 0 }, /* mm1 : 19 */
1.60 + { REG_FPU_OFFSET + 2, 0 }, /* mm2 : 20 */
1.61 + { REG_FPU_OFFSET + 3, 0 }, /* mm3 : 21 */
1.62 + { REG_FPU_OFFSET + 4, 0 }, /* mm4 : 22 */
1.63 + { REG_FPU_OFFSET + 5, 0 }, /* mm5 : 23 */
1.64 + { REG_FPU_OFFSET + 6, 0 }, /* mm6 : 24 */
1.65 + { REG_FPU_OFFSET + 7, 0 } /* mm7 : 25 */
1.66 + };
1.67 +
1.68 +/* REGISTER TABLE: size, type, and name of every register in the
1.69 + * CPU. Does not include MSRs since the are, after all,
1.70 + * model specific. */
1.71 +static struct {
1.72 + unsigned int size;
1.73 + enum x86_reg_type type;
1.74 + unsigned int alias;
1.75 + char mnemonic[8];
1.76 +} ia32_reg_table[NUM_X86_REGS + 2] = {
1.77 + { 0, 0, 0, "" },
1.78 + /* REG_DWORD_OFFSET */
1.79 + { REG_DWORD_SIZE, reg_gen | reg_ret, 0, "eax" },
1.80 + { REG_DWORD_SIZE, reg_gen | reg_count, 0, "ecx" },
1.81 + { REG_DWORD_SIZE, reg_gen, 0, "edx" },
1.82 + { REG_DWORD_SIZE, reg_gen, 0, "ebx" },
1.83 + /* REG_ESP_INDEX */
1.84 + { REG_DWORD_SIZE, reg_gen | reg_sp, 0, "esp" },
1.85 + { REG_DWORD_SIZE, reg_gen | reg_fp, 0, "ebp" },
1.86 + { REG_DWORD_SIZE, reg_gen | reg_src, 0, "esi" },
1.87 + { REG_DWORD_SIZE, reg_gen | reg_dest, 0, "edi" },
1.88 + /* REG_WORD_OFFSET */
1.89 + { REG_WORD_SIZE, reg_gen | reg_ret, 3, "ax" },
1.90 + { REG_WORD_SIZE, reg_gen | reg_count, 6, "cx" },
1.91 + { REG_WORD_SIZE, reg_gen, 9, "dx" },
1.92 + { REG_WORD_SIZE, reg_gen, 12, "bx" },
1.93 + { REG_WORD_SIZE, reg_gen | reg_sp, 13, "sp" },
1.94 + { REG_WORD_SIZE, reg_gen | reg_fp, 14, "bp" },
1.95 + { REG_WORD_SIZE, reg_gen | reg_src, 15, "si" },
1.96 + { REG_WORD_SIZE, reg_gen | reg_dest, 16, "di" },
1.97 + /* REG_BYTE_OFFSET */
1.98 + { REG_BYTE_SIZE, reg_gen, 1, "al" },
1.99 + { REG_BYTE_SIZE, reg_gen, 4, "cl" },
1.100 + { REG_BYTE_SIZE, reg_gen, 7, "dl" },
1.101 + { REG_BYTE_SIZE, reg_gen, 10, "bl" },
1.102 + { REG_BYTE_SIZE, reg_gen, 2, "ah" },
1.103 + { REG_BYTE_SIZE, reg_gen, 5, "ch" },
1.104 + { REG_BYTE_SIZE, reg_gen, 8, "dh" },
1.105 + { REG_BYTE_SIZE, reg_gen, 11, "bh" },
1.106 + /* REG_MMX_OFFSET */
1.107 + { REG_MMX_SIZE, reg_simd, 18, "mm0" },
1.108 + { REG_MMX_SIZE, reg_simd, 19, "mm1" },
1.109 + { REG_MMX_SIZE, reg_simd, 20, "mm2" },
1.110 + { REG_MMX_SIZE, reg_simd, 21, "mm3" },
1.111 + { REG_MMX_SIZE, reg_simd, 22, "mm4" },
1.112 + { REG_MMX_SIZE, reg_simd, 23, "mm5" },
1.113 + { REG_MMX_SIZE, reg_simd, 24, "mm6" },
1.114 + { REG_MMX_SIZE, reg_simd, 25, "mm7" },
1.115 + /* REG_SIMD_OFFSET */
1.116 + { REG_SIMD_SIZE, reg_simd, 0, "xmm0" },
1.117 + { REG_SIMD_SIZE, reg_simd, 0, "xmm1" },
1.118 + { REG_SIMD_SIZE, reg_simd, 0, "xmm2" },
1.119 + { REG_SIMD_SIZE, reg_simd, 0, "xmm3" },
1.120 + { REG_SIMD_SIZE, reg_simd, 0, "xmm4" },
1.121 + { REG_SIMD_SIZE, reg_simd, 0, "xmm5" },
1.122 + { REG_SIMD_SIZE, reg_simd, 0, "xmm6" },
1.123 + { REG_SIMD_SIZE, reg_simd, 0, "xmm7" },
1.124 + /* REG_DEBUG_OFFSET */
1.125 + { REG_DEBUG_SIZE, reg_sys, 0, "dr0" },
1.126 + { REG_DEBUG_SIZE, reg_sys, 0, "dr1" },
1.127 + { REG_DEBUG_SIZE, reg_sys, 0, "dr2" },
1.128 + { REG_DEBUG_SIZE, reg_sys, 0, "dr3" },
1.129 + { REG_DEBUG_SIZE, reg_sys, 0, "dr4" },
1.130 + { REG_DEBUG_SIZE, reg_sys, 0, "dr5" },
1.131 + { REG_DEBUG_SIZE, reg_sys, 0, "dr6" },
1.132 + { REG_DEBUG_SIZE, reg_sys, 0, "dr7" },
1.133 + /* REG_CTRL_OFFSET */
1.134 + { REG_CTRL_SIZE, reg_sys, 0, "cr0" },
1.135 + { REG_CTRL_SIZE, reg_sys, 0, "cr1" },
1.136 + { REG_CTRL_SIZE, reg_sys, 0, "cr2" },
1.137 + { REG_CTRL_SIZE, reg_sys, 0, "cr3" },
1.138 + { REG_CTRL_SIZE, reg_sys, 0, "cr4" },
1.139 + { REG_CTRL_SIZE, reg_sys, 0, "cr5" },
1.140 + { REG_CTRL_SIZE, reg_sys, 0, "cr6" },
1.141 + { REG_CTRL_SIZE, reg_sys, 0, "cr7" },
1.142 + /* REG_TEST_OFFSET */
1.143 + { REG_TEST_SIZE, reg_sys, 0, "tr0" },
1.144 + { REG_TEST_SIZE, reg_sys, 0, "tr1" },
1.145 + { REG_TEST_SIZE, reg_sys, 0, "tr2" },
1.146 + { REG_TEST_SIZE, reg_sys, 0, "tr3" },
1.147 + { REG_TEST_SIZE, reg_sys, 0, "tr4" },
1.148 + { REG_TEST_SIZE, reg_sys, 0, "tr5" },
1.149 + { REG_TEST_SIZE, reg_sys, 0, "tr6" },
1.150 + { REG_TEST_SIZE, reg_sys, 0, "tr7" },
1.151 + /* REG_SEG_OFFSET */
1.152 + { REG_SEG_SIZE, reg_seg, 0, "es" },
1.153 + { REG_SEG_SIZE, reg_seg, 0, "cs" },
1.154 + { REG_SEG_SIZE, reg_seg, 0, "ss" },
1.155 + { REG_SEG_SIZE, reg_seg, 0, "ds" },
1.156 + { REG_SEG_SIZE, reg_seg, 0, "fs" },
1.157 + { REG_SEG_SIZE, reg_seg, 0, "gs" },
1.158 + /* REG_LDTR_INDEX */
1.159 + { REG_DWORD_SIZE, reg_sys, 0, "ldtr" },
1.160 + /* REG_GDTR_INDEX */
1.161 + { REG_DWORD_SIZE, reg_sys, 0, "gdtr" },
1.162 + /* REG_FPU_OFFSET */
1.163 + { REG_FPU_SIZE, reg_fpu, 0, "st(0)" },
1.164 + { REG_FPU_SIZE, reg_fpu, 0, "st(1)" },
1.165 + { REG_FPU_SIZE, reg_fpu, 0, "st(2)" },
1.166 + { REG_FPU_SIZE, reg_fpu, 0, "st(3)" },
1.167 + { REG_FPU_SIZE, reg_fpu, 0, "st(4)" },
1.168 + { REG_FPU_SIZE, reg_fpu, 0, "st(5)" },
1.169 + { REG_FPU_SIZE, reg_fpu, 0, "st(6)" },
1.170 + { REG_FPU_SIZE, reg_fpu, 0, "st(7)" },
1.171 + /* REG_FLAGS_INDEX : 81 */
1.172 + { REG_FLAGS_SIZE, reg_cond, 0, "eflags" },
1.173 + /* REG_FPCTRL_INDEX : 82*/
1.174 + { REG_FPCTRL_SIZE, reg_fpu | reg_sys, 0, "fpctrl" },
1.175 + /* REG_FPSTATUS_INDEX : 83*/
1.176 + { REG_FPSTATUS_SIZE, reg_fpu | reg_sys, 0, "fpstat" },
1.177 + /* REG_FPTAG_INDEX : 84 */
1.178 + { REG_FPTAG_SIZE, reg_fpu | reg_sys, 0, "fptag" },
1.179 + /* REG_EIP_INDEX : 85 */
1.180 + { REG_EIP_SIZE, reg_pc, 0, "eip" },
1.181 + /* REG_IP_INDEX : 86 */
1.182 + { REG_IP_SIZE, reg_pc, 17, "ip" },
1.183 + /* REG_IDTR_INDEX : 87 */
1.184 + { REG_DWORD_SIZE, reg_sys, 0, "idtr" },
1.185 + /* REG_MXCSG_INDEX : SSE Control Reg : 88 */
1.186 + { REG_DWORD_SIZE, reg_sys | reg_simd, 0, "mxcsr" },
1.187 + /* REG_TR_INDEX : Task Register : 89 */
1.188 + { 16 + 64, reg_sys, 0, "tr" },
1.189 + /* REG_CSMSR_INDEX : SYSENTER_CS_MSR : 90 */
1.190 + { REG_DWORD_SIZE, reg_sys, 0, "cs_msr" },
1.191 + /* REG_ESPMSR_INDEX : SYSENTER_ESP_MSR : 91 */
1.192 + { REG_DWORD_SIZE, reg_sys, 0, "esp_msr" },
1.193 + /* REG_EIPMSR_INDEX : SYSENTER_EIP_MSR : 92 */
1.194 + { REG_DWORD_SIZE, reg_sys, 0, "eip_msr" },
1.195 + { 0 }
1.196 + };
1.197 +
1.198 +
1.199 +static size_t sz_regtable = NUM_X86_REGS + 1;
1.200 +
1.201 +
1.202 +void ia32_handle_register( x86_reg_t *reg, size_t id ) {
1.203 + unsigned int alias;
1.204 + if (! id || id > sz_regtable ) {
1.205 + return;
1.206 + }
1.207 +
1.208 + memset( reg, 0, sizeof(x86_reg_t) );
1.209 +
1.210 + strncpy( reg->name, ia32_reg_table[id].mnemonic, MAX_REGNAME );
1.211 +
1.212 + reg->type = ia32_reg_table[id].type;
1.213 + reg->size = ia32_reg_table[id].size;
1.214 +
1.215 + alias = ia32_reg_table[id].alias;
1.216 + if ( alias ) {
1.217 + reg->alias = ia32_reg_aliases[alias].alias;
1.218 + reg->shift = ia32_reg_aliases[alias].shift;
1.219 + }
1.220 + reg->id = id;
1.221 +
1.222 + return;
1.223 +}
1.224 +
1.225 +size_t ia32_true_register_id( size_t id ) {
1.226 + size_t reg;
1.227 +
1.228 + if (! id || id > sz_regtable ) {
1.229 + return 0;
1.230 + }
1.231 +
1.232 + reg = id;
1.233 + if (ia32_reg_table[reg].alias) {
1.234 + reg = ia32_reg_aliases[ia32_reg_table[reg].alias].alias;
1.235 + }
1.236 + return reg;
1.237 +}
