The Tor Browser / annotate

toolkit/crashreporter/google-breakpad/src/third_party/libdisasm/ia32_reg.c@6474c204b198 (annotated)

toolkit/crashreporter/google-breakpad/src/third_party/libdisasm/ia32_reg.c

Wed, 31 Dec 2014 06:09:35 +0100

author
Michael Schloh von Bennewitz <michael@schloh.com>
date
Wed, 31 Dec 2014 06:09:35 +0100
changeset 0
6474c204b198
permissions
-rw-r--r--

Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.

michael@0 1 #include <stdlib.h>
michael@0 2 #include <string.h>
michael@0 3
michael@0 4 #include "ia32_reg.h"
michael@0 5 #include "ia32_insn.h"
michael@0 6
michael@0 7 #define NUM_X86_REGS 92
michael@0 8
michael@0 9 /* register sizes */
michael@0 10 #define REG_DWORD_SIZE 4
michael@0 11 #define REG_WORD_SIZE 2
michael@0 12 #define REG_BYTE_SIZE 1
michael@0 13 #define REG_MMX_SIZE 8
michael@0 14 #define REG_SIMD_SIZE 16
michael@0 15 #define REG_DEBUG_SIZE 4
michael@0 16 #define REG_CTRL_SIZE 4
michael@0 17 #define REG_TEST_SIZE 4
michael@0 18 #define REG_SEG_SIZE 2
michael@0 19 #define REG_FPU_SIZE 10
michael@0 20 #define REG_FLAGS_SIZE 4
michael@0 21 #define REG_FPCTRL_SIZE 2
michael@0 22 #define REG_FPSTATUS_SIZE 2
michael@0 23 #define REG_FPTAG_SIZE 2
michael@0 24 #define REG_EIP_SIZE 4
michael@0 25 #define REG_IP_SIZE 2
michael@0 26
michael@0 27 /* REGISTER ALIAS TABLE:
michael@0 28 *
michael@0 29 * NOTE: the MMX register mapping is fixed to the physical registers
michael@0 30 * used by the FPU. The floating FP stack does not effect the location
michael@0 31 * of the MMX registers, so this aliasing is not 100% accurate.
michael@0 32 * */
michael@0 33 static struct {
michael@0 34 unsigned char alias; /* id of register this is an alias for */
michael@0 35 unsigned char shift; /* # of bits register must be shifted */
michael@0 36 } ia32_reg_aliases[] = {
michael@0 37 { 0,0 },
michael@0 38 { REG_DWORD_OFFSET, 0 }, /* al : 1 */
michael@0 39 { REG_DWORD_OFFSET, 8 }, /* ah : 2 */
michael@0 40 { REG_DWORD_OFFSET, 0 }, /* ax : 3 */
michael@0 41 { REG_DWORD_OFFSET + 1, 0 }, /* cl : 4 */
michael@0 42 { REG_DWORD_OFFSET + 1, 8 }, /* ch : 5 */
michael@0 43 { REG_DWORD_OFFSET + 1, 0 }, /* cx : 6 */
michael@0 44 { REG_DWORD_OFFSET + 2, 0 }, /* dl : 7 */
michael@0 45 { REG_DWORD_OFFSET + 2, 8 }, /* dh : 8 */
michael@0 46 { REG_DWORD_OFFSET + 2, 0 }, /* dx : 9 */
michael@0 47 { REG_DWORD_OFFSET + 3, 0 }, /* bl : 10 */
michael@0 48 { REG_DWORD_OFFSET + 3, 8 }, /* bh : 11 */
michael@0 49 { REG_DWORD_OFFSET + 3, 0 }, /* bx : 12 */
michael@0 50 { REG_DWORD_OFFSET + 4, 0 }, /* sp : 13 */
michael@0 51 { REG_DWORD_OFFSET + 5, 0 }, /* bp : 14 */
michael@0 52 { REG_DWORD_OFFSET + 6, 0 }, /* si : 15 */
michael@0 53 { REG_DWORD_OFFSET + 7, 0 }, /* di : 16 */
michael@0 54 { REG_EIP_INDEX, 0 }, /* ip : 17 */
michael@0 55 { REG_FPU_OFFSET, 0 }, /* mm0 : 18 */
michael@0 56 { REG_FPU_OFFSET + 1, 0 }, /* mm1 : 19 */
michael@0 57 { REG_FPU_OFFSET + 2, 0 }, /* mm2 : 20 */
michael@0 58 { REG_FPU_OFFSET + 3, 0 }, /* mm3 : 21 */
michael@0 59 { REG_FPU_OFFSET + 4, 0 }, /* mm4 : 22 */
michael@0 60 { REG_FPU_OFFSET + 5, 0 }, /* mm5 : 23 */
michael@0 61 { REG_FPU_OFFSET + 6, 0 }, /* mm6 : 24 */
michael@0 62 { REG_FPU_OFFSET + 7, 0 } /* mm7 : 25 */
michael@0 63 };
michael@0 64
michael@0 65 /* REGISTER TABLE: size, type, and name of every register in the
michael@0 66 * CPU. Does not include MSRs since the are, after all,
michael@0 67 * model specific. */
michael@0 68 static struct {
michael@0 69 unsigned int size;
michael@0 70 enum x86_reg_type type;
michael@0 71 unsigned int alias;
michael@0 72 char mnemonic[8];
michael@0 73 } ia32_reg_table[NUM_X86_REGS + 2] = {
michael@0 74 { 0, 0, 0, "" },
michael@0 75 /* REG_DWORD_OFFSET */
michael@0 76 { REG_DWORD_SIZE, reg_gen | reg_ret, 0, "eax" },
michael@0 77 { REG_DWORD_SIZE, reg_gen | reg_count, 0, "ecx" },
michael@0 78 { REG_DWORD_SIZE, reg_gen, 0, "edx" },
michael@0 79 { REG_DWORD_SIZE, reg_gen, 0, "ebx" },
michael@0 80 /* REG_ESP_INDEX */
michael@0 81 { REG_DWORD_SIZE, reg_gen | reg_sp, 0, "esp" },
michael@0 82 { REG_DWORD_SIZE, reg_gen | reg_fp, 0, "ebp" },
michael@0 83 { REG_DWORD_SIZE, reg_gen | reg_src, 0, "esi" },
michael@0 84 { REG_DWORD_SIZE, reg_gen | reg_dest, 0, "edi" },
michael@0 85 /* REG_WORD_OFFSET */
michael@0 86 { REG_WORD_SIZE, reg_gen | reg_ret, 3, "ax" },
michael@0 87 { REG_WORD_SIZE, reg_gen | reg_count, 6, "cx" },
michael@0 88 { REG_WORD_SIZE, reg_gen, 9, "dx" },
michael@0 89 { REG_WORD_SIZE, reg_gen, 12, "bx" },
michael@0 90 { REG_WORD_SIZE, reg_gen | reg_sp, 13, "sp" },
michael@0 91 { REG_WORD_SIZE, reg_gen | reg_fp, 14, "bp" },
michael@0 92 { REG_WORD_SIZE, reg_gen | reg_src, 15, "si" },
michael@0 93 { REG_WORD_SIZE, reg_gen | reg_dest, 16, "di" },
michael@0 94 /* REG_BYTE_OFFSET */
michael@0 95 { REG_BYTE_SIZE, reg_gen, 1, "al" },
michael@0 96 { REG_BYTE_SIZE, reg_gen, 4, "cl" },
michael@0 97 { REG_BYTE_SIZE, reg_gen, 7, "dl" },
michael@0 98 { REG_BYTE_SIZE, reg_gen, 10, "bl" },
michael@0 99 { REG_BYTE_SIZE, reg_gen, 2, "ah" },
michael@0 100 { REG_BYTE_SIZE, reg_gen, 5, "ch" },
michael@0 101 { REG_BYTE_SIZE, reg_gen, 8, "dh" },
michael@0 102 { REG_BYTE_SIZE, reg_gen, 11, "bh" },
michael@0 103 /* REG_MMX_OFFSET */
michael@0 104 { REG_MMX_SIZE, reg_simd, 18, "mm0" },
michael@0 105 { REG_MMX_SIZE, reg_simd, 19, "mm1" },
michael@0 106 { REG_MMX_SIZE, reg_simd, 20, "mm2" },
michael@0 107 { REG_MMX_SIZE, reg_simd, 21, "mm3" },
michael@0 108 { REG_MMX_SIZE, reg_simd, 22, "mm4" },
michael@0 109 { REG_MMX_SIZE, reg_simd, 23, "mm5" },
michael@0 110 { REG_MMX_SIZE, reg_simd, 24, "mm6" },
michael@0 111 { REG_MMX_SIZE, reg_simd, 25, "mm7" },
michael@0 112 /* REG_SIMD_OFFSET */
michael@0 113 { REG_SIMD_SIZE, reg_simd, 0, "xmm0" },
michael@0 114 { REG_SIMD_SIZE, reg_simd, 0, "xmm1" },
michael@0 115 { REG_SIMD_SIZE, reg_simd, 0, "xmm2" },
michael@0 116 { REG_SIMD_SIZE, reg_simd, 0, "xmm3" },
michael@0 117 { REG_SIMD_SIZE, reg_simd, 0, "xmm4" },
michael@0 118 { REG_SIMD_SIZE, reg_simd, 0, "xmm5" },
michael@0 119 { REG_SIMD_SIZE, reg_simd, 0, "xmm6" },
michael@0 120 { REG_SIMD_SIZE, reg_simd, 0, "xmm7" },
michael@0 121 /* REG_DEBUG_OFFSET */
michael@0 122 { REG_DEBUG_SIZE, reg_sys, 0, "dr0" },
michael@0 123 { REG_DEBUG_SIZE, reg_sys, 0, "dr1" },
michael@0 124 { REG_DEBUG_SIZE, reg_sys, 0, "dr2" },
michael@0 125 { REG_DEBUG_SIZE, reg_sys, 0, "dr3" },
michael@0 126 { REG_DEBUG_SIZE, reg_sys, 0, "dr4" },
michael@0 127 { REG_DEBUG_SIZE, reg_sys, 0, "dr5" },
michael@0 128 { REG_DEBUG_SIZE, reg_sys, 0, "dr6" },
michael@0 129 { REG_DEBUG_SIZE, reg_sys, 0, "dr7" },
michael@0 130 /* REG_CTRL_OFFSET */
michael@0 131 { REG_CTRL_SIZE, reg_sys, 0, "cr0" },
michael@0 132 { REG_CTRL_SIZE, reg_sys, 0, "cr1" },
michael@0 133 { REG_CTRL_SIZE, reg_sys, 0, "cr2" },
michael@0 134 { REG_CTRL_SIZE, reg_sys, 0, "cr3" },
michael@0 135 { REG_CTRL_SIZE, reg_sys, 0, "cr4" },
michael@0 136 { REG_CTRL_SIZE, reg_sys, 0, "cr5" },
michael@0 137 { REG_CTRL_SIZE, reg_sys, 0, "cr6" },
michael@0 138 { REG_CTRL_SIZE, reg_sys, 0, "cr7" },
michael@0 139 /* REG_TEST_OFFSET */
michael@0 140 { REG_TEST_SIZE, reg_sys, 0, "tr0" },
michael@0 141 { REG_TEST_SIZE, reg_sys, 0, "tr1" },
michael@0 142 { REG_TEST_SIZE, reg_sys, 0, "tr2" },
michael@0 143 { REG_TEST_SIZE, reg_sys, 0, "tr3" },
michael@0 144 { REG_TEST_SIZE, reg_sys, 0, "tr4" },
michael@0 145 { REG_TEST_SIZE, reg_sys, 0, "tr5" },
michael@0 146 { REG_TEST_SIZE, reg_sys, 0, "tr6" },
michael@0 147 { REG_TEST_SIZE, reg_sys, 0, "tr7" },
michael@0 148 /* REG_SEG_OFFSET */
michael@0 149 { REG_SEG_SIZE, reg_seg, 0, "es" },
michael@0 150 { REG_SEG_SIZE, reg_seg, 0, "cs" },
michael@0 151 { REG_SEG_SIZE, reg_seg, 0, "ss" },
michael@0 152 { REG_SEG_SIZE, reg_seg, 0, "ds" },
michael@0 153 { REG_SEG_SIZE, reg_seg, 0, "fs" },
michael@0 154 { REG_SEG_SIZE, reg_seg, 0, "gs" },
michael@0 155 /* REG_LDTR_INDEX */
michael@0 156 { REG_DWORD_SIZE, reg_sys, 0, "ldtr" },
michael@0 157 /* REG_GDTR_INDEX */
michael@0 158 { REG_DWORD_SIZE, reg_sys, 0, "gdtr" },
michael@0 159 /* REG_FPU_OFFSET */
michael@0 160 { REG_FPU_SIZE, reg_fpu, 0, "st(0)" },
michael@0 161 { REG_FPU_SIZE, reg_fpu, 0, "st(1)" },
michael@0 162 { REG_FPU_SIZE, reg_fpu, 0, "st(2)" },
michael@0 163 { REG_FPU_SIZE, reg_fpu, 0, "st(3)" },
michael@0 164 { REG_FPU_SIZE, reg_fpu, 0, "st(4)" },
michael@0 165 { REG_FPU_SIZE, reg_fpu, 0, "st(5)" },
michael@0 166 { REG_FPU_SIZE, reg_fpu, 0, "st(6)" },
michael@0 167 { REG_FPU_SIZE, reg_fpu, 0, "st(7)" },
michael@0 168 /* REG_FLAGS_INDEX : 81 */
michael@0 169 { REG_FLAGS_SIZE, reg_cond, 0, "eflags" },
michael@0 170 /* REG_FPCTRL_INDEX : 82*/
michael@0 171 { REG_FPCTRL_SIZE, reg_fpu | reg_sys, 0, "fpctrl" },
michael@0 172 /* REG_FPSTATUS_INDEX : 83*/
michael@0 173 { REG_FPSTATUS_SIZE, reg_fpu | reg_sys, 0, "fpstat" },
michael@0 174 /* REG_FPTAG_INDEX : 84 */
michael@0 175 { REG_FPTAG_SIZE, reg_fpu | reg_sys, 0, "fptag" },
michael@0 176 /* REG_EIP_INDEX : 85 */
michael@0 177 { REG_EIP_SIZE, reg_pc, 0, "eip" },
michael@0 178 /* REG_IP_INDEX : 86 */
michael@0 179 { REG_IP_SIZE, reg_pc, 17, "ip" },
michael@0 180 /* REG_IDTR_INDEX : 87 */
michael@0 181 { REG_DWORD_SIZE, reg_sys, 0, "idtr" },
michael@0 182 /* REG_MXCSG_INDEX : SSE Control Reg : 88 */
michael@0 183 { REG_DWORD_SIZE, reg_sys | reg_simd, 0, "mxcsr" },
michael@0 184 /* REG_TR_INDEX : Task Register : 89 */
michael@0 185 { 16 + 64, reg_sys, 0, "tr" },
michael@0 186 /* REG_CSMSR_INDEX : SYSENTER_CS_MSR : 90 */
michael@0 187 { REG_DWORD_SIZE, reg_sys, 0, "cs_msr" },
michael@0 188 /* REG_ESPMSR_INDEX : SYSENTER_ESP_MSR : 91 */
michael@0 189 { REG_DWORD_SIZE, reg_sys, 0, "esp_msr" },
michael@0 190 /* REG_EIPMSR_INDEX : SYSENTER_EIP_MSR : 92 */
michael@0 191 { REG_DWORD_SIZE, reg_sys, 0, "eip_msr" },
michael@0 192 { 0 }
michael@0 193 };
michael@0 194
michael@0 195
michael@0 196 static size_t sz_regtable = NUM_X86_REGS + 1;
michael@0 197
michael@0 198
michael@0 199 void ia32_handle_register( x86_reg_t *reg, size_t id ) {
michael@0 200 unsigned int alias;
michael@0 201 if (! id || id > sz_regtable ) {
michael@0 202 return;
michael@0 203 }
michael@0 204
michael@0 205 memset( reg, 0, sizeof(x86_reg_t) );
michael@0 206
michael@0 207 strncpy( reg->name, ia32_reg_table[id].mnemonic, MAX_REGNAME );
michael@0 208
michael@0 209 reg->type = ia32_reg_table[id].type;
michael@0 210 reg->size = ia32_reg_table[id].size;
michael@0 211
michael@0 212 alias = ia32_reg_table[id].alias;
michael@0 213 if ( alias ) {
michael@0 214 reg->alias = ia32_reg_aliases[alias].alias;
michael@0 215 reg->shift = ia32_reg_aliases[alias].shift;
michael@0 216 }
michael@0 217 reg->id = id;
michael@0 218
michael@0 219 return;
michael@0 220 }
michael@0 221
michael@0 222 size_t ia32_true_register_id( size_t id ) {
michael@0 223 size_t reg;
michael@0 224
michael@0 225 if (! id || id > sz_regtable ) {
michael@0 226 return 0;
michael@0 227 }
michael@0 228
michael@0 229 reg = id;
michael@0 230 if (ia32_reg_table[reg].alias) {
michael@0 231 reg = ia32_reg_aliases[ia32_reg_table[reg].alias].alias;
michael@0 232 }
michael@0 233 return reg;
michael@0 234 }

Mercurial Repository: The Tor Browser

Europalab SCM Repository Server

mercurial