xpcom/reflect/xptcall/src/md/unix/xptcstubs_asm_mips.S

Thu, 22 Jan 2015 13:21:57 +0100

author
Michael Schloh von Bennewitz <michael@schloh.com>
date
Thu, 22 Jan 2015 13:21:57 +0100
branch
TOR_BUG_9701
changeset 15
b8a032363ba2
permissions
-rw-r--r--

Incorporate requested changes from Mozilla in review:
https://bugzilla.mozilla.org/show_bug.cgi?id=1123480#c6

     1 /* -*- Mode: asm; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- */
     2 /* This Source Code Form is subject to the terms of the Mozilla Public
     3  * License, v. 2.0. If a copy of the MPL was not distributed with this
     4  * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
     6 /* This code is for MIPS using the O32 ABI. */
     8 #ifdef ANDROID
     9 #include <asm/regdef.h>
    10 #include <asm/asm.h>
    11 #include <machine/asm.h>
    12 #else
    13 #include <sys/regdef.h>
    14 #include <sys/asm.h>
    15 #endif
    17 # NARGSAVE is the argument space in the callers frame, including extra
    18 # 'shadowed' space for the argument registers. The minimum of 4
    19 # argument slots is sometimes predefined in the header files.
    20 #ifndef NARGSAVE
    21 #define NARGSAVE 4
    22 #endif
    24 #define LOCALSZ 2	/* gp, ra */
    25 #define FRAMESZ ((((NARGSAVE+LOCALSZ)*SZREG)+ALSZ)&ALMASK)
    27 #define RAOFF (FRAMESZ - (1*SZREG))
    28 #define GPOFF (FRAMESZ - (2*SZREG))
    30 #define A0OFF (FRAMESZ + (0*SZREG))
    31 #define A1OFF (FRAMESZ + (1*SZREG))
    32 #define A2OFF (FRAMESZ + (2*SZREG))
    33 #define A3OFF (FRAMESZ + (3*SZREG))
    35 	.text
    37 #define STUB_ENTRY(x)						\
    38 	.if x < 10;						\
    39 	.globl	_ZN14nsXPTCStubBase5Stub ##x ##Ev;		\
    40 	.type	_ZN14nsXPTCStubBase5Stub ##x ##Ev,@function;	\
    41 	.aent	_ZN14nsXPTCStubBase5Stub ##x ##Ev,0;		\
    42 _ZN14nsXPTCStubBase5Stub ##x ##Ev:;				\
    43 	SETUP_GP;						\
    44 	li	t0,x;						\
    45 	b	sharedstub;					\
    46 	.elseif x < 100;					\
    47 	.globl	_ZN14nsXPTCStubBase6Stub ##x ##Ev;		\
    48 	.type	_ZN14nsXPTCStubBase6Stub ##x ##Ev,@function;	\
    49 	.aent	_ZN14nsXPTCStubBase6Stub ##x ##Ev,0;		\
    50 _ZN14nsXPTCStubBase6Stub ##x ##Ev:;				\
    51 	SETUP_GP;						\
    52 	li	t0,x;						\
    53 	b	sharedstub;					\
    54 	.elseif x < 1000;					\
    55 	.globl	_ZN14nsXPTCStubBase7Stub ##x ##Ev;		\
    56 	.type	_ZN14nsXPTCStubBase7Stub ##x ##Ev,@function;	\
    57 	.aent	_ZN14nsXPTCStubBase7Stub ##x ##Ev,0;		\
    58 _ZN14nsXPTCStubBase7Stub ##x ##Ev:;				\
    59 	SETUP_GP;						\
    60 	li	t0,x;						\
    61 	b	sharedstub;					\
    62 	.else;							\
    63 	.err;							\
    64 	.endif
    66 # SENTINEL_ENTRY is handled in the cpp file.
    67 #define SENTINEL_ENTRY(x)
    69 #
    70 # open a dummy frame for the function entries
    71 #
    72 	.align	2
    73 	.type	dummy,@function
    74 	.ent	dummy, 0
    75 	.frame	sp, FRAMESZ, ra 
    76 dummy:
    77 	SETUP_GP
    79 #include "xptcstubsdef.inc"
    81 sharedstub:
    82 	subu	sp, FRAMESZ
    84 	# specify the save register mask for gp, ra, a0-a3
    85 	.mask 0x900000F0, RAOFF-FRAMESZ
    87 	sw	ra, RAOFF(sp)
    88 	SAVE_GP(GPOFF)
    90 	# Micro-optimization: a0 is already loaded, and its slot gets
    91 	# ignored by PrepareAndDispatch, so no need to save it here.
    92 	# sw	a0, A0OFF(sp)
    93 	sw	a1, A1OFF(sp)
    94 	sw	a2, A2OFF(sp)
    95 	sw	a3, A3OFF(sp)
    97 	la	t9, PrepareAndDispatch
    99 	# t0 is methodIndex
   100 	move	a1, t0
   101 	# have a2 point to the begin of the argument space on stack
   102 	addiu	a2, sp, FRAMESZ
   104 	# PrepareAndDispatch(that, methodIndex, args)
   105 	jalr	t9
   107 	# Micro-optimization: Using jalr explicitly has the side-effect
   108 	# of not triggering .cprestore. This is ok because we have no
   109 	# gp reference below this point. It also allows better
   110 	# instruction sscheduling.
   111 	# lw	gp, GPOFF(fp)
   113  	lw	ra, RAOFF(sp)
   114 	addiu	sp, FRAMESZ
   115 	j	ra
   116 	END(dummy)

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