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media/libopus/silk/arm/macros_armv5e.h@6474c204b198 (annotated)

media/libopus/silk/arm/macros_armv5e.h

Wed, 31 Dec 2014 06:09:35 +0100

author
Michael Schloh von Bennewitz <michael@schloh.com>
date
Wed, 31 Dec 2014 06:09:35 +0100
changeset 0
6474c204b198
permissions
-rw-r--r--

Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.

michael@0 1 /***********************************************************************
michael@0 2 Copyright (c) 2006-2011, Skype Limited. All rights reserved.
michael@0 3 Copyright (c) 2013 Parrot
michael@0 4 Redistribution and use in source and binary forms, with or without
michael@0 5 modification, are permitted provided that the following conditions
michael@0 6 are met:
michael@0 7 - Redistributions of source code must retain the above copyright notice,
michael@0 8 this list of conditions and the following disclaimer.
michael@0 9 - Redistributions in binary form must reproduce the above copyright
michael@0 10 notice, this list of conditions and the following disclaimer in the
michael@0 11 documentation and/or other materials provided with the distribution.
michael@0 12 - Neither the name of Internet Society, IETF or IETF Trust, nor the
michael@0 13 names of specific contributors, may be used to endorse or promote
michael@0 14 products derived from this software without specific prior written
michael@0 15 permission.
michael@0 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
michael@0 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
michael@0 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
michael@0 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
michael@0 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
michael@0 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
michael@0 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
michael@0 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
michael@0 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
michael@0 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
michael@0 26 POSSIBILITY OF SUCH DAMAGE.
michael@0 27 ***********************************************************************/
michael@0 28
michael@0 29 #ifndef SILK_MACROS_ARMv5E_H
michael@0 30 #define SILK_MACROS_ARMv5E_H
michael@0 31
michael@0 32 /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */
michael@0 33 #undef silk_SMULWB
michael@0 34 static OPUS_INLINE opus_int32 silk_SMULWB_armv5e(opus_int32 a, opus_int16 b)
michael@0 35 {
michael@0 36 int res;
michael@0 37 __asm__(
michael@0 38 "#silk_SMULWB\n\t"
michael@0 39 "smulwb %0, %1, %2\n\t"
michael@0 40 : "=r"(res)
michael@0 41 : "r"(a), "r"(b)
michael@0 42 );
michael@0 43 return res;
michael@0 44 }
michael@0 45 #define silk_SMULWB(a, b) (silk_SMULWB_armv5e(a, b))
michael@0 46
michael@0 47 /* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */
michael@0 48 #undef silk_SMLAWB
michael@0 49 static OPUS_INLINE opus_int32 silk_SMLAWB_armv5e(opus_int32 a, opus_int32 b,
michael@0 50 opus_int16 c)
michael@0 51 {
michael@0 52 int res;
michael@0 53 __asm__(
michael@0 54 "#silk_SMLAWB\n\t"
michael@0 55 "smlawb %0, %1, %2, %3\n\t"
michael@0 56 : "=r"(res)
michael@0 57 : "r"(b), "r"(c), "r"(a)
michael@0 58 );
michael@0 59 return res;
michael@0 60 }
michael@0 61 #define silk_SMLAWB(a, b, c) (silk_SMLAWB_armv5e(a, b, c))
michael@0 62
michael@0 63 /* (a32 * (b32 >> 16)) >> 16 */
michael@0 64 #undef silk_SMULWT
michael@0 65 static OPUS_INLINE opus_int32 silk_SMULWT_armv5e(opus_int32 a, opus_int32 b)
michael@0 66 {
michael@0 67 int res;
michael@0 68 __asm__(
michael@0 69 "#silk_SMULWT\n\t"
michael@0 70 "smulwt %0, %1, %2\n\t"
michael@0 71 : "=r"(res)
michael@0 72 : "r"(a), "r"(b)
michael@0 73 );
michael@0 74 return res;
michael@0 75 }
michael@0 76 #define silk_SMULWT(a, b) (silk_SMULWT_armv5e(a, b))
michael@0 77
michael@0 78 /* a32 + (b32 * (c32 >> 16)) >> 16 */
michael@0 79 #undef silk_SMLAWT
michael@0 80 static OPUS_INLINE opus_int32 silk_SMLAWT_armv5e(opus_int32 a, opus_int32 b,
michael@0 81 opus_int32 c)
michael@0 82 {
michael@0 83 int res;
michael@0 84 __asm__(
michael@0 85 "#silk_SMLAWT\n\t"
michael@0 86 "smlawt %0, %1, %2, %3\n\t"
michael@0 87 : "=r"(res)
michael@0 88 : "r"(b), "r"(c), "r"(a)
michael@0 89 );
michael@0 90 return res;
michael@0 91 }
michael@0 92 #define silk_SMLAWT(a, b, c) (silk_SMLAWT_armv5e(a, b, c))
michael@0 93
michael@0 94 /* (opus_int32)((opus_int16)(a3))) * (opus_int32)((opus_int16)(b32)) output have to be 32bit int */
michael@0 95 #undef silk_SMULBB
michael@0 96 static OPUS_INLINE opus_int32 silk_SMULBB_armv5e(opus_int32 a, opus_int32 b)
michael@0 97 {
michael@0 98 int res;
michael@0 99 __asm__(
michael@0 100 "#silk_SMULBB\n\t"
michael@0 101 "smulbb %0, %1, %2\n\t"
michael@0 102 : "=r"(res)
michael@0 103 : "%r"(a), "r"(b)
michael@0 104 );
michael@0 105 return res;
michael@0 106 }
michael@0 107 #define silk_SMULBB(a, b) (silk_SMULBB_armv5e(a, b))
michael@0 108
michael@0 109 /* a32 + (opus_int32)((opus_int16)(b32)) * (opus_int32)((opus_int16)(c32)) output have to be 32bit int */
michael@0 110 #undef silk_SMLABB
michael@0 111 static OPUS_INLINE opus_int32 silk_SMLABB_armv5e(opus_int32 a, opus_int32 b,
michael@0 112 opus_int32 c)
michael@0 113 {
michael@0 114 int res;
michael@0 115 __asm__(
michael@0 116 "#silk_SMLABB\n\t"
michael@0 117 "smlabb %0, %1, %2, %3\n\t"
michael@0 118 : "=r"(res)
michael@0 119 : "%r"(b), "r"(c), "r"(a)
michael@0 120 );
michael@0 121 return res;
michael@0 122 }
michael@0 123 #define silk_SMLABB(a, b, c) (silk_SMLABB_armv5e(a, b, c))
michael@0 124
michael@0 125 /* (opus_int32)((opus_int16)(a32)) * (b32 >> 16) */
michael@0 126 #undef silk_SMULBT
michael@0 127 static OPUS_INLINE opus_int32 silk_SMULBT_armv5e(opus_int32 a, opus_int32 b)
michael@0 128 {
michael@0 129 int res;
michael@0 130 __asm__(
michael@0 131 "#silk_SMULBT\n\t"
michael@0 132 "smulbt %0, %1, %2\n\t"
michael@0 133 : "=r"(res)
michael@0 134 : "r"(a), "r"(b)
michael@0 135 );
michael@0 136 return res;
michael@0 137 }
michael@0 138 #define silk_SMULBT(a, b) (silk_SMULBT_armv5e(a, b))
michael@0 139
michael@0 140 /* a32 + (opus_int32)((opus_int16)(b32)) * (c32 >> 16) */
michael@0 141 #undef silk_SMLABT
michael@0 142 static OPUS_INLINE opus_int32 silk_SMLABT_armv5e(opus_int32 a, opus_int32 b,
michael@0 143 opus_int32 c)
michael@0 144 {
michael@0 145 int res;
michael@0 146 __asm__(
michael@0 147 "#silk_SMLABT\n\t"
michael@0 148 "smlabt %0, %1, %2, %3\n\t"
michael@0 149 : "=r"(res)
michael@0 150 : "r"(b), "r"(c), "r"(a)
michael@0 151 );
michael@0 152 return res;
michael@0 153 }
michael@0 154 #define silk_SMLABT(a, b, c) (silk_SMLABT_armv5e(a, b, c))
michael@0 155
michael@0 156 /* add/subtract with output saturated */
michael@0 157 #undef silk_ADD_SAT32
michael@0 158 static OPUS_INLINE opus_int32 silk_ADD_SAT32_armv5e(opus_int32 a, opus_int32 b)
michael@0 159 {
michael@0 160 int res;
michael@0 161 __asm__(
michael@0 162 "#silk_ADD_SAT32\n\t"
michael@0 163 "qadd %0, %1, %2\n\t"
michael@0 164 : "=r"(res)
michael@0 165 : "%r"(a), "r"(b)
michael@0 166 );
michael@0 167 return res;
michael@0 168 }
michael@0 169 #define silk_ADD_SAT32(a, b) (silk_ADD_SAT32_armv5e(a, b))
michael@0 170
michael@0 171 #undef silk_SUB_SAT32
michael@0 172 static OPUS_INLINE opus_int32 silk_SUB_SAT32_armv5e(opus_int32 a, opus_int32 b)
michael@0 173 {
michael@0 174 int res;
michael@0 175 __asm__(
michael@0 176 "#silk_SUB_SAT32\n\t"
michael@0 177 "qsub %0, %1, %2\n\t"
michael@0 178 : "=r"(res)
michael@0 179 : "r"(a), "r"(b)
michael@0 180 );
michael@0 181 return res;
michael@0 182 }
michael@0 183 #define silk_SUB_SAT32(a, b) (silk_SUB_SAT32_armv5e(a, b))
michael@0 184
michael@0 185 #undef silk_CLZ16
michael@0 186 static OPUS_INLINE opus_int32 silk_CLZ16_armv5(opus_int16 in16)
michael@0 187 {
michael@0 188 int res;
michael@0 189 __asm__(
michael@0 190 "#silk_CLZ16\n\t"
michael@0 191 "clz %0, %1;\n"
michael@0 192 : "=r"(res)
michael@0 193 : "r"(in16<<16|0x8000)
michael@0 194 );
michael@0 195 return res;
michael@0 196 }
michael@0 197 #define silk_CLZ16(in16) (silk_CLZ16_armv5(in16))
michael@0 198
michael@0 199 #undef silk_CLZ32
michael@0 200 static OPUS_INLINE opus_int32 silk_CLZ32_armv5(opus_int32 in32)
michael@0 201 {
michael@0 202 int res;
michael@0 203 __asm__(
michael@0 204 "#silk_CLZ32\n\t"
michael@0 205 "clz %0, %1\n\t"
michael@0 206 : "=r"(res)
michael@0 207 : "r"(in32)
michael@0 208 );
michael@0 209 return res;
michael@0 210 }
michael@0 211 #define silk_CLZ32(in32) (silk_CLZ32_armv5(in32))
michael@0 212
michael@0 213 #endif /* SILK_MACROS_ARMv5E_H */

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