1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/media/libtheora/lib/x86/x86state.c Wed Dec 31 06:09:35 2014 +0100
1.3 @@ -0,0 +1,95 @@
1.4 +/********************************************************************
1.5 + * *
1.6 + * THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *
1.7 + * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
1.8 + * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
1.9 + * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
1.10 + * *
1.11 + * THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009 *
1.12 + * by the Xiph.Org Foundation and contributors http://www.xiph.org/ *
1.13 + * *
1.14 + ********************************************************************
1.15 +
1.16 + function:
1.17 + last mod: $Id: x86state.c 17421 2010-09-22 16:46:18Z giles $
1.18 +
1.19 + ********************************************************************/
1.20 +
1.21 +#include "x86int.h"
1.22 +
1.23 +#if defined(OC_X86_ASM)
1.24 +
1.25 +/*This table has been modified from OC_FZIG_ZAG by baking a 4x4 transpose into
1.26 + each quadrant of the destination.*/
1.27 +static const unsigned char OC_FZIG_ZAG_MMX[128]={
1.28 + 0, 8, 1, 2, 9,16,24,17,
1.29 + 10, 3,32,11,18,25, 4,12,
1.30 + 5,26,19,40,33,34,41,48,
1.31 + 27, 6,13,20,28,21,14, 7,
1.32 + 56,49,42,35,43,50,57,36,
1.33 + 15,22,29,30,23,44,37,58,
1.34 + 51,59,38,45,52,31,60,53,
1.35 + 46,39,47,54,61,62,55,63,
1.36 + 64,64,64,64,64,64,64,64,
1.37 + 64,64,64,64,64,64,64,64,
1.38 + 64,64,64,64,64,64,64,64,
1.39 + 64,64,64,64,64,64,64,64,
1.40 + 64,64,64,64,64,64,64,64,
1.41 + 64,64,64,64,64,64,64,64,
1.42 + 64,64,64,64,64,64,64,64,
1.43 + 64,64,64,64,64,64,64,64
1.44 +};
1.45 +
1.46 +/*This table has been modified from OC_FZIG_ZAG by baking an 8x8 transpose into
1.47 + the destination.*/
1.48 +static const unsigned char OC_FZIG_ZAG_SSE2[128]={
1.49 + 0, 8, 1, 2, 9,16,24,17,
1.50 + 10, 3, 4,11,18,25,32,40,
1.51 + 33,26,19,12, 5, 6,13,20,
1.52 + 27,34,41,48,56,49,42,35,
1.53 + 28,21,14, 7,15,22,29,36,
1.54 + 43,50,57,58,51,44,37,30,
1.55 + 23,31,38,45,52,59,60,53,
1.56 + 46,39,47,54,61,62,55,63,
1.57 + 64,64,64,64,64,64,64,64,
1.58 + 64,64,64,64,64,64,64,64,
1.59 + 64,64,64,64,64,64,64,64,
1.60 + 64,64,64,64,64,64,64,64,
1.61 + 64,64,64,64,64,64,64,64,
1.62 + 64,64,64,64,64,64,64,64,
1.63 + 64,64,64,64,64,64,64,64,
1.64 + 64,64,64,64,64,64,64,64
1.65 +};
1.66 +
1.67 +void oc_state_accel_init_x86(oc_theora_state *_state){
1.68 + oc_state_accel_init_c(_state);
1.69 + _state->cpu_flags=oc_cpu_flags_get();
1.70 +# if defined(OC_STATE_USE_VTABLE)
1.71 + if(_state->cpu_flags&OC_CPU_X86_MMX){
1.72 + _state->opt_vtable.frag_copy=oc_frag_copy_mmx;
1.73 + _state->opt_vtable.frag_copy_list=oc_frag_copy_list_mmx;
1.74 + _state->opt_vtable.frag_recon_intra=oc_frag_recon_intra_mmx;
1.75 + _state->opt_vtable.frag_recon_inter=oc_frag_recon_inter_mmx;
1.76 + _state->opt_vtable.frag_recon_inter2=oc_frag_recon_inter2_mmx;
1.77 + _state->opt_vtable.idct8x8=oc_idct8x8_mmx;
1.78 + _state->opt_vtable.state_frag_recon=oc_state_frag_recon_mmx;
1.79 + _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmx;
1.80 + _state->opt_vtable.state_loop_filter_frag_rows=
1.81 + oc_state_loop_filter_frag_rows_mmx;
1.82 + _state->opt_vtable.restore_fpu=oc_restore_fpu_mmx;
1.83 + _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_MMX;
1.84 + }
1.85 + if(_state->cpu_flags&OC_CPU_X86_MMXEXT){
1.86 + _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmxext;
1.87 + _state->opt_vtable.state_loop_filter_frag_rows=
1.88 + oc_state_loop_filter_frag_rows_mmxext;
1.89 + }
1.90 + if(_state->cpu_flags&OC_CPU_X86_SSE2){
1.91 + _state->opt_vtable.idct8x8=oc_idct8x8_sse2;
1.92 +# endif
1.93 + _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_SSE2;
1.94 +# if defined(OC_STATE_USE_VTABLE)
1.95 + }
1.96 +# endif
1.97 +}
1.98 +#endif
