media/libtheora/lib/x86/x86state.c@6474c204b198
media/libtheora/lib/x86/x86state.c
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
1 /********************************************************************
2 * *
3 * THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *
4 * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
5 * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
6 * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
7 * *
8 * THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009 *
9 * by the Xiph.Org Foundation and contributors http://www.xiph.org/ *
10 * *
11 ********************************************************************
13 function:
14 last mod: $Id: x86state.c 17421 2010-09-22 16:46:18Z giles $
16 ********************************************************************/
18 #include "x86int.h"
20 #if defined(OC_X86_ASM)
22 /*This table has been modified from OC_FZIG_ZAG by baking a 4x4 transpose into
23 each quadrant of the destination.*/
24 static const unsigned char OC_FZIG_ZAG_MMX[128]={
25 0, 8, 1, 2, 9,16,24,17,
26 10, 3,32,11,18,25, 4,12,
27 5,26,19,40,33,34,41,48,
28 27, 6,13,20,28,21,14, 7,
29 56,49,42,35,43,50,57,36,
30 15,22,29,30,23,44,37,58,
31 51,59,38,45,52,31,60,53,
32 46,39,47,54,61,62,55,63,
33 64,64,64,64,64,64,64,64,
34 64,64,64,64,64,64,64,64,
35 64,64,64,64,64,64,64,64,
36 64,64,64,64,64,64,64,64,
37 64,64,64,64,64,64,64,64,
38 64,64,64,64,64,64,64,64,
39 64,64,64,64,64,64,64,64,
40 64,64,64,64,64,64,64,64
41 };
43 /*This table has been modified from OC_FZIG_ZAG by baking an 8x8 transpose into
44 the destination.*/
45 static const unsigned char OC_FZIG_ZAG_SSE2[128]={
46 0, 8, 1, 2, 9,16,24,17,
47 10, 3, 4,11,18,25,32,40,
48 33,26,19,12, 5, 6,13,20,
49 27,34,41,48,56,49,42,35,
50 28,21,14, 7,15,22,29,36,
51 43,50,57,58,51,44,37,30,
52 23,31,38,45,52,59,60,53,
53 46,39,47,54,61,62,55,63,
54 64,64,64,64,64,64,64,64,
55 64,64,64,64,64,64,64,64,
56 64,64,64,64,64,64,64,64,
57 64,64,64,64,64,64,64,64,
58 64,64,64,64,64,64,64,64,
59 64,64,64,64,64,64,64,64,
60 64,64,64,64,64,64,64,64,
61 64,64,64,64,64,64,64,64
62 };
64 void oc_state_accel_init_x86(oc_theora_state *_state){
65 oc_state_accel_init_c(_state);
66 _state->cpu_flags=oc_cpu_flags_get();
67 # if defined(OC_STATE_USE_VTABLE)
68 if(_state->cpu_flags&OC_CPU_X86_MMX){
69 _state->opt_vtable.frag_copy=oc_frag_copy_mmx;
70 _state->opt_vtable.frag_copy_list=oc_frag_copy_list_mmx;
71 _state->opt_vtable.frag_recon_intra=oc_frag_recon_intra_mmx;
72 _state->opt_vtable.frag_recon_inter=oc_frag_recon_inter_mmx;
73 _state->opt_vtable.frag_recon_inter2=oc_frag_recon_inter2_mmx;
74 _state->opt_vtable.idct8x8=oc_idct8x8_mmx;
75 _state->opt_vtable.state_frag_recon=oc_state_frag_recon_mmx;
76 _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmx;
77 _state->opt_vtable.state_loop_filter_frag_rows=
78 oc_state_loop_filter_frag_rows_mmx;
79 _state->opt_vtable.restore_fpu=oc_restore_fpu_mmx;
80 _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_MMX;
81 }
82 if(_state->cpu_flags&OC_CPU_X86_MMXEXT){
83 _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmxext;
84 _state->opt_vtable.state_loop_filter_frag_rows=
85 oc_state_loop_filter_frag_rows_mmxext;
86 }
87 if(_state->cpu_flags&OC_CPU_X86_SSE2){
88 _state->opt_vtable.idct8x8=oc_idct8x8_sse2;
89 # endif
90 _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_SSE2;
91 # if defined(OC_STATE_USE_VTABLE)
92 }
93 # endif
94 }
95 #endif
