media/libtheora/lib/x86/x86state.c@6474c204b198 (annotated)
media/libtheora/lib/x86/x86state.c
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
| michael@0 | 1 | /******************************************************************** |
| michael@0 | 2 | * * |
| michael@0 | 3 | * THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. * |
| michael@0 | 4 | * USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS * |
| michael@0 | 5 | * GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE * |
| michael@0 | 6 | * IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. * |
| michael@0 | 7 | * * |
| michael@0 | 8 | * THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2009 * |
| michael@0 | 9 | * by the Xiph.Org Foundation and contributors http://www.xiph.org/ * |
| michael@0 | 10 | * * |
| michael@0 | 11 | ******************************************************************** |
| michael@0 | 12 | |
| michael@0 | 13 | function: |
| michael@0 | 14 | last mod: $Id: x86state.c 17421 2010-09-22 16:46:18Z giles $ |
| michael@0 | 15 | |
| michael@0 | 16 | ********************************************************************/ |
| michael@0 | 17 | |
| michael@0 | 18 | #include "x86int.h" |
| michael@0 | 19 | |
| michael@0 | 20 | #if defined(OC_X86_ASM) |
| michael@0 | 21 | |
| michael@0 | 22 | /*This table has been modified from OC_FZIG_ZAG by baking a 4x4 transpose into |
| michael@0 | 23 | each quadrant of the destination.*/ |
| michael@0 | 24 | static const unsigned char OC_FZIG_ZAG_MMX[128]={ |
| michael@0 | 25 | 0, 8, 1, 2, 9,16,24,17, |
| michael@0 | 26 | 10, 3,32,11,18,25, 4,12, |
| michael@0 | 27 | 5,26,19,40,33,34,41,48, |
| michael@0 | 28 | 27, 6,13,20,28,21,14, 7, |
| michael@0 | 29 | 56,49,42,35,43,50,57,36, |
| michael@0 | 30 | 15,22,29,30,23,44,37,58, |
| michael@0 | 31 | 51,59,38,45,52,31,60,53, |
| michael@0 | 32 | 46,39,47,54,61,62,55,63, |
| michael@0 | 33 | 64,64,64,64,64,64,64,64, |
| michael@0 | 34 | 64,64,64,64,64,64,64,64, |
| michael@0 | 35 | 64,64,64,64,64,64,64,64, |
| michael@0 | 36 | 64,64,64,64,64,64,64,64, |
| michael@0 | 37 | 64,64,64,64,64,64,64,64, |
| michael@0 | 38 | 64,64,64,64,64,64,64,64, |
| michael@0 | 39 | 64,64,64,64,64,64,64,64, |
| michael@0 | 40 | 64,64,64,64,64,64,64,64 |
| michael@0 | 41 | }; |
| michael@0 | 42 | |
| michael@0 | 43 | /*This table has been modified from OC_FZIG_ZAG by baking an 8x8 transpose into |
| michael@0 | 44 | the destination.*/ |
| michael@0 | 45 | static const unsigned char OC_FZIG_ZAG_SSE2[128]={ |
| michael@0 | 46 | 0, 8, 1, 2, 9,16,24,17, |
| michael@0 | 47 | 10, 3, 4,11,18,25,32,40, |
| michael@0 | 48 | 33,26,19,12, 5, 6,13,20, |
| michael@0 | 49 | 27,34,41,48,56,49,42,35, |
| michael@0 | 50 | 28,21,14, 7,15,22,29,36, |
| michael@0 | 51 | 43,50,57,58,51,44,37,30, |
| michael@0 | 52 | 23,31,38,45,52,59,60,53, |
| michael@0 | 53 | 46,39,47,54,61,62,55,63, |
| michael@0 | 54 | 64,64,64,64,64,64,64,64, |
| michael@0 | 55 | 64,64,64,64,64,64,64,64, |
| michael@0 | 56 | 64,64,64,64,64,64,64,64, |
| michael@0 | 57 | 64,64,64,64,64,64,64,64, |
| michael@0 | 58 | 64,64,64,64,64,64,64,64, |
| michael@0 | 59 | 64,64,64,64,64,64,64,64, |
| michael@0 | 60 | 64,64,64,64,64,64,64,64, |
| michael@0 | 61 | 64,64,64,64,64,64,64,64 |
| michael@0 | 62 | }; |
| michael@0 | 63 | |
| michael@0 | 64 | void oc_state_accel_init_x86(oc_theora_state *_state){ |
| michael@0 | 65 | oc_state_accel_init_c(_state); |
| michael@0 | 66 | _state->cpu_flags=oc_cpu_flags_get(); |
| michael@0 | 67 | # if defined(OC_STATE_USE_VTABLE) |
| michael@0 | 68 | if(_state->cpu_flags&OC_CPU_X86_MMX){ |
| michael@0 | 69 | _state->opt_vtable.frag_copy=oc_frag_copy_mmx; |
| michael@0 | 70 | _state->opt_vtable.frag_copy_list=oc_frag_copy_list_mmx; |
| michael@0 | 71 | _state->opt_vtable.frag_recon_intra=oc_frag_recon_intra_mmx; |
| michael@0 | 72 | _state->opt_vtable.frag_recon_inter=oc_frag_recon_inter_mmx; |
| michael@0 | 73 | _state->opt_vtable.frag_recon_inter2=oc_frag_recon_inter2_mmx; |
| michael@0 | 74 | _state->opt_vtable.idct8x8=oc_idct8x8_mmx; |
| michael@0 | 75 | _state->opt_vtable.state_frag_recon=oc_state_frag_recon_mmx; |
| michael@0 | 76 | _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmx; |
| michael@0 | 77 | _state->opt_vtable.state_loop_filter_frag_rows= |
| michael@0 | 78 | oc_state_loop_filter_frag_rows_mmx; |
| michael@0 | 79 | _state->opt_vtable.restore_fpu=oc_restore_fpu_mmx; |
| michael@0 | 80 | _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_MMX; |
| michael@0 | 81 | } |
| michael@0 | 82 | if(_state->cpu_flags&OC_CPU_X86_MMXEXT){ |
| michael@0 | 83 | _state->opt_vtable.loop_filter_init=oc_loop_filter_init_mmxext; |
| michael@0 | 84 | _state->opt_vtable.state_loop_filter_frag_rows= |
| michael@0 | 85 | oc_state_loop_filter_frag_rows_mmxext; |
| michael@0 | 86 | } |
| michael@0 | 87 | if(_state->cpu_flags&OC_CPU_X86_SSE2){ |
| michael@0 | 88 | _state->opt_vtable.idct8x8=oc_idct8x8_sse2; |
| michael@0 | 89 | # endif |
| michael@0 | 90 | _state->opt_data.dct_fzig_zag=OC_FZIG_ZAG_SSE2; |
| michael@0 | 91 | # if defined(OC_STATE_USE_VTABLE) |
| michael@0 | 92 | } |
| michael@0 | 93 | # endif |
| michael@0 | 94 | } |
| michael@0 | 95 | #endif |
