media/libopus/silk/arm/macros_armv4.h@6474c204b198 (annotated)
media/libopus/silk/arm/macros_armv4.h
Wed, 31 Dec 2014 06:09:35 +0100
- author
- Michael Schloh von Bennewitz <michael@schloh.com>
- date
- Wed, 31 Dec 2014 06:09:35 +0100
- changeset 0
- 6474c204b198
- permissions
- -rw-r--r--
Cloned upstream origin tor-browser at tor-browser-31.3.0esr-4.5-1-build1
revision ID fc1c9ff7c1b2defdbc039f12214767608f46423f for hacking purpose.
| michael@0 | 1 | /*********************************************************************** |
| michael@0 | 2 | Copyright (C) 2013 Xiph.Org Foundation and contributors. |
| michael@0 | 3 | Redistribution and use in source and binary forms, with or without |
| michael@0 | 4 | modification, are permitted provided that the following conditions |
| michael@0 | 5 | are met: |
| michael@0 | 6 | - Redistributions of source code must retain the above copyright notice, |
| michael@0 | 7 | this list of conditions and the following disclaimer. |
| michael@0 | 8 | - Redistributions in binary form must reproduce the above copyright |
| michael@0 | 9 | notice, this list of conditions and the following disclaimer in the |
| michael@0 | 10 | documentation and/or other materials provided with the distribution. |
| michael@0 | 11 | - Neither the name of Internet Society, IETF or IETF Trust, nor the |
| michael@0 | 12 | names of specific contributors, may be used to endorse or promote |
| michael@0 | 13 | products derived from this software without specific prior written |
| michael@0 | 14 | permission. |
| michael@0 | 15 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| michael@0 | 16 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| michael@0 | 17 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| michael@0 | 18 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| michael@0 | 19 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| michael@0 | 20 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| michael@0 | 21 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| michael@0 | 22 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| michael@0 | 23 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| michael@0 | 24 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| michael@0 | 25 | POSSIBILITY OF SUCH DAMAGE. |
| michael@0 | 26 | ***********************************************************************/ |
| michael@0 | 27 | |
| michael@0 | 28 | #ifndef SILK_MACROS_ARMv4_H |
| michael@0 | 29 | #define SILK_MACROS_ARMv4_H |
| michael@0 | 30 | |
| michael@0 | 31 | /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */ |
| michael@0 | 32 | #undef silk_SMULWB |
| michael@0 | 33 | static OPUS_INLINE opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b) |
| michael@0 | 34 | { |
| michael@0 | 35 | unsigned rd_lo; |
| michael@0 | 36 | int rd_hi; |
| michael@0 | 37 | __asm__( |
| michael@0 | 38 | "#silk_SMULWB\n\t" |
| michael@0 | 39 | "smull %0, %1, %2, %3\n\t" |
| michael@0 | 40 | : "=&r"(rd_lo), "=&r"(rd_hi) |
| michael@0 | 41 | : "%r"(a), "r"(b<<16) |
| michael@0 | 42 | ); |
| michael@0 | 43 | return rd_hi; |
| michael@0 | 44 | } |
| michael@0 | 45 | #define silk_SMULWB(a, b) (silk_SMULWB_armv4(a, b)) |
| michael@0 | 46 | |
| michael@0 | 47 | /* a32 + (b32 * (opus_int32)((opus_int16)(c32))) >> 16 output have to be 32bit int */ |
| michael@0 | 48 | #undef silk_SMLAWB |
| michael@0 | 49 | #define silk_SMLAWB(a, b, c) ((a) + silk_SMULWB(b, c)) |
| michael@0 | 50 | |
| michael@0 | 51 | /* (a32 * (b32 >> 16)) >> 16 */ |
| michael@0 | 52 | #undef silk_SMULWT |
| michael@0 | 53 | static OPUS_INLINE opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b) |
| michael@0 | 54 | { |
| michael@0 | 55 | unsigned rd_lo; |
| michael@0 | 56 | int rd_hi; |
| michael@0 | 57 | __asm__( |
| michael@0 | 58 | "#silk_SMULWT\n\t" |
| michael@0 | 59 | "smull %0, %1, %2, %3\n\t" |
| michael@0 | 60 | : "=&r"(rd_lo), "=&r"(rd_hi) |
| michael@0 | 61 | : "%r"(a), "r"(b&~0xFFFF) |
| michael@0 | 62 | ); |
| michael@0 | 63 | return rd_hi; |
| michael@0 | 64 | } |
| michael@0 | 65 | #define silk_SMULWT(a, b) (silk_SMULWT_armv4(a, b)) |
| michael@0 | 66 | |
| michael@0 | 67 | /* a32 + (b32 * (c32 >> 16)) >> 16 */ |
| michael@0 | 68 | #undef silk_SMLAWT |
| michael@0 | 69 | #define silk_SMLAWT(a, b, c) ((a) + silk_SMULWT(b, c)) |
| michael@0 | 70 | |
| michael@0 | 71 | /* (a32 * b32) >> 16 */ |
| michael@0 | 72 | #undef silk_SMULWW |
| michael@0 | 73 | static OPUS_INLINE opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b) |
| michael@0 | 74 | { |
| michael@0 | 75 | unsigned rd_lo; |
| michael@0 | 76 | int rd_hi; |
| michael@0 | 77 | __asm__( |
| michael@0 | 78 | "#silk_SMULWW\n\t" |
| michael@0 | 79 | "smull %0, %1, %2, %3\n\t" |
| michael@0 | 80 | : "=&r"(rd_lo), "=&r"(rd_hi) |
| michael@0 | 81 | : "%r"(a), "r"(b) |
| michael@0 | 82 | ); |
| michael@0 | 83 | return (rd_hi<<16)+(rd_lo>>16); |
| michael@0 | 84 | } |
| michael@0 | 85 | #define silk_SMULWW(a, b) (silk_SMULWW_armv4(a, b)) |
| michael@0 | 86 | |
| michael@0 | 87 | #undef silk_SMLAWW |
| michael@0 | 88 | static OPUS_INLINE opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b, |
| michael@0 | 89 | opus_int32 c) |
| michael@0 | 90 | { |
| michael@0 | 91 | unsigned rd_lo; |
| michael@0 | 92 | int rd_hi; |
| michael@0 | 93 | __asm__( |
| michael@0 | 94 | "#silk_SMLAWW\n\t" |
| michael@0 | 95 | "smull %0, %1, %2, %3\n\t" |
| michael@0 | 96 | : "=&r"(rd_lo), "=&r"(rd_hi) |
| michael@0 | 97 | : "%r"(b), "r"(c) |
| michael@0 | 98 | ); |
| michael@0 | 99 | return a+(rd_hi<<16)+(rd_lo>>16); |
| michael@0 | 100 | } |
| michael@0 | 101 | #define silk_SMLAWW(a, b, c) (silk_SMLAWW_armv4(a, b, c)) |
| michael@0 | 102 | |
| michael@0 | 103 | #endif /* SILK_MACROS_ARMv4_H */ |
